pipelineADC中MDAC尾电流的确定

各位大神：     请教关于MDAC中运放尾电流怎么计算?
     设计指标是10bit，100MHz，VFS=1V，电源电压VDD=1.8V。想设计成七级1.5bit/级+3bit FlashADC。
     在计算设计参数的时候，采样电容、Au、GBW计算出来了。尾电流不知道怎么算，是用压摆率来算吗，SR=I/C。具体应该怎么算呢?
     新人求助，卡在这了，求指点

參考:
if your OP use Folded-Cascaded OP
SR=I/C , SR time 知道 and C 知道
the tail current 就是 2I.
total OP current is 4I (4 DC Path).

Thank you very much for your reply.
My OP use  telescopic cascode.I＝SR*C.The sampling rate is 100MSPS,so the T=10ns.The effective time of the two-phase non-overlapping clock φ1φ2 is 1/2T=5ns.Then the setup time is 1/4T=2.5ns.
SR=2.5ns? If not,how to caculate the SR?Does the C refer to the C of next stage here?
Thax.

SR=2.5ns too long,
SR=1/4T =1.25ns is OK,
equivalent Capacitance at X2 mode
-->The total C of next stage + feedback factor(1/2) * This Stage Capacitor

   I sill have some confusion.The SR is on the order of ns,and the capacitance is on the order of fF.The value of  I (=SR*C) is so small.For example,in an essay,SR=1.25ns,C=150fF+1/2*300fF,but the tail current given is 3mA.   (I'm a newcomer to ADC. So  I found an essay about 10bit pipelineADC  .And  I want to design a new ADC which sampling rate is 100MSPS  according to the given example.)
   If I know the power dissipation and power supply, can I just estimate and distribute the current of each stage?
So thx.

以前FUYIBIN这个ID有个pipeline设计帖子，我曾经就参考这个做的，10bit， 100M，结果还是很靠谱。当然也没有追求低功耗，面积小。

HO！ Pieplined ADC 10-bit 100MHz has big current is Normal,
No any suprise！
3mA is Normal！
Also
Pipelined ADC Capacitor can be scaleiing stage by stage,
so second stage will be 1.5mA
third stage will be 0.75mA
and so on.
so 50% total current is consumed by first stage.
Again:
3mA is very Normal because 100MHz is very fast conversion rate in ADC design

3mA is very Normal in Pipelined ADC because 100MHz is very fast conversion rate.
also,
the Pipelined ADC Capacitor can be scaling stage by stage,
so 3mA tail current in first stage,
1.5mA tial current in second stage,
and so on.
so most current is consumed by first stage.
3mA in first stage is no any suprise for pipelined ADC.

   那我去找找，也不是说要达到很高的性能指标，就是想通过看一个例子，然后再改一改指标按照例子设计。感觉这样对ADC的理解会更透彻些。光看论文老是看着看着发现本以为看懂的又看迷糊了^_^

   What I mean is that the obtained tail current by caculating(I =SR * C) is far from 3mA given in the example.

SR time =1.25nsec
CV=Ixt
300fF*1V=I*1.25nsec
I=240uA
Example 3mA ?
Can not understand ?

Example tail curent is dominated by small settling time
and need  very Big OP Unity-gain frequency
To 1GHz unity-gain frequency is normal.
the 3mA is not calculated by SR Limitation constraint

   Thank you very much for your patient explainning！

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