VCO的理想VerilogA模型

1. module vco1 (out, in);
   
2. 
   
3. input in; voltage in;                                // input terminal
   
4. output out; voltage out;                        // output terminal
   
5. parameter real vmin=0;                                // input voltage that corresponds to minimum output frequency
   
6. parameter real vmax=vmin+1 from (vmin:inf);        // input voltage that corresponds to maximum output frequency
   
7. parameter real fmin=1 from (0:inf);                // minimum output frequency
   
8. parameter real fmax=2*fmin from (fmin:inf);        // maximum output frequency
   
9. parameter real vl=-1;                                // high output voltage
   
10. parameter real vh=1;                                // low output voltage
    
11. parameter real tt=0.01/fmax from (0:inf);        // output transition time
    
12. parameter real ttol=1u/fmax from (0:1/fmax);        // time tolerance
    
13. real freq, phase;
    
14. integer n;
    
15. 
    
16. analog begin
    
17.     // compute the freq from the input voltage
    
18.     freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;
    
19. 
    
20.     // bound the frequency (this is optional)
    
21.     if (freq > fmax) freq = fmax;
    
22.     if (freq < fmin) freq = fmin;
    
23. 
    
24.     // bound the time step to assure no cycles are skipped
    
25.     $bound_step(0.6/freq);
    
26. 
    
27.     // phase is the integral of the freq modulo 2p
    
28.     phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
    
29. 
    
30.     // identify the point where switching occurs
    
31.     @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol))
    
32.         n = (phase >= -`M_PI/2) && (phase < `M_PI/2);
    
33. 
    
34.     // generate the output
    
35.     V(out) <+ transition(n ? vh : vl, 0, tt);
    
36. end
    
37. endmodule

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