VDD and Lmin for GPDKs

what would be the VDD (Supply Voltage) for gpdk180, gpdk090 and gpdk045....?
Is VDD is a constant or can be varied over a range...?
What are the constraints to be taken into consideration for deciding VDD for a specific Technology...?
In gpdk090 the Lmin is 100 nm rather than 90 nm ... What would be the reason behind it...?
Please do enlighten me in this concern......
Thanks in advance.......

For each semiconductor process generation, the main purpose of the dimension shrinkage is to low the die area and power consumption. So, VDD will be decreased due to:
1. Gate oxide became thinner. So, the upper limit of Vgs, Vgd and Vgb will become lower. So, VDD must be decreased.
2. P-N Junction breakdown voltage will be lower due to shallow junction.
3. MOS channel will be much easier to punch through due to shorter channel length.
As for the reason of Lmin=100nm of gpdf90, it might be the reason that the MOS device (especially NMOS) is easier to punch through if L=90nm is applied.

Thank you very much for your response michang5342.......
As far as my simulations in cadence virtuoso is concern What should be the the VDD value
(For gpdk180, gpdk090, gpdk045)........?
Please help me out................

For the technology you had listed, there were several type devices, IO device, core device ...
In general, VDD was named as the core device power supply voltage. You can get it from the design documents.
As I remembered, the VDD for gpdk180 was 1.8V, gpdk090  was 1.2V (or 1.1V)...

Thanks a lot michang5342.....................

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