PFD型PLL设计遇到的问题

只有当VCO输出频率fv和PLL输入频率fr相等时，PLL才会锁定。

那应该怎样衡量这个相近呢?难道不是用锁定范围来衡量么?

3# 小小xxl

PLL的输出频率在VCO的频率范围内。VCO的输出与PLL的参考输入通过鉴相器产生一个误差电压，通过LPF后产生VCO的调谐电压控制VCO的输出，如果你的环路设计正确的话，环路最终会锁定，从而得到你想要的频率。改变参考频率，可以得到不同的频率输出。如果你的环路设计的不好，环路就有可能永远失锁。

哦，谢谢哈，我明白了，只要输入的频率在输出范围内就可以锁定啊！我可以在问个问题么，是不是锁定范围没有公式来求得啊?还有你们是怎样确定VCO的增益的呢?

VCO  的静态和动态特性有一些概念要理解清楚
Hold range: 在相位误差接近最大时，VCO能保持相位锁定时的频率范围，对CP PLL来讲，理论上无穷大，只要你的KV最够大。
Pull-in range:失锁后再次锁定时的频率捕捉范围，对于CP PLL 也是理论无穷大。
Pull-out range:动态特性，突然加一个频率阶跃，环路失锁，这时候的频率范围是pull-out范围。
Lock range:两个鉴相频率足够接近，环路再进过一个鉴相周期就可以锁定，这个频率范围叫锁定范围。
上面这些概念对于不同类型的鉴相器，结果不一样。

谢谢楼上的耐心指点。其实我一直关系的是这些范围对我们的PLL设计有什么知道意义呢?比如说锁定范围对我们的参数设定有什么影响呢?

这个问题感觉挺绕人，可以参见best的书

只有两频率相等时才锁定，但是频率不等时能给出误差电压，所以我觉得只要voc能调节过去锁相环能最终锁上

呵呵，我也觉得很绕的啊！

恩，就是啊。我也觉得是这样子的！呵呵，哪就先这样认为算了！哈哈

best book has good option on this

http://www.google.com.hk/search?sourceid=chrome&ie=UTF-8&q=PFD+PLL+theoryPhase Frequency Detectors (PFD)
The phase detector generates the error signal required in the feedback loop of the synthesizer. The majority of PLL ASICs use a circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 6. Compared with mixers or XOR gates, which can only resolve phase differences in the +/- p range, the PFD can resolve phase differences in the +/- 2p range or more (typically “frequency difference” is used to describe a phase difference of more than 2p, hence the term “phase frequency detector.” This circuit shortens transient switching times and performs the function in a simple and elegant digital circuit.

The PFD compares the reference signal Fr with that of the divided down VCO signal (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, phase detect, and phase locked mode. When the phase difference is greater than ±2p, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.)
The loop filter integrates this current and the result is a continuously  hanging control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2p.

http://www.google.com.hk/search?sourceid=chrome&ie=UTF-8&q=PFD+PLL+theoryPhase Frequency Detectors (PFD)
The phase detector generates the error signal required in the feedback loop of the synthesizer. The majority of PLL ASICs use a circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 6. Compared with mixers or XOR gates, which can only resolve phase differences in the +/- p range, the PFD can resolve phase differences in the +/- 2p range or more (typically “frequency difference” is used to describe a phase difference of more than 2p, hence the term “phase frequency detector.” This circuit shortens transient switching times and performs the function in a simple and elegant digital circuit.

The PFD compares the reference signal Fr with that of the divided down VCO signal (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, phase detect, and phase locked mode. When the phase difference is greater than ±2p, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.)
The loop filter integrates this current and the result is a continuously  hanging control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2p.

不错！

我想请问一个问题，对于环路滤波器的带宽有没有参考的确认方法或者公式来计算一个带宽值！

看看吧

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