求几篇cdr相关的jssc
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1. J. Lee et al., “Analysis and Modeling of Bang-Bang Clock and Data Recovery
Circuits”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, pp.
1571-1580.
2. J. Sonntag et al., “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s
Binary Links”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, August 2006, pp.
1867-1875.
3. P. K. Hanumolu, et al., “A Wide-Tracking Range Clock and Data Recovery Circuit”,
IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, February 2008, pp. 425-439.
1. J. Lee et al., “Analysis and Modeling of Bang-Bang Clock and Data Recovery
Circuits”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004, pp.
1571-1580.
2. J. Sonntag et al., “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s
Binary Links”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 8, August 2006, pp.
1867-1875.
3. P. K. Hanumolu, et al., “A Wide-Tracking Range Clock and Data Recovery Circuit”,
IEEE Journal of Solid-State Circuits, Vol. 43, No. 2, February 2008, pp. 425-439.
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