请教高手关于PLL里面sigma_delta modulator问题

The D-S modulators for the fractional-N synthesizer may not use the decimation filter to

suppress the high-frequency noise in the digital domain since the PLL with integer-N

dividers does not allow an intermediate level between N and N + 1. Therefore, the clock

frequency of the oversampling modulator must be same as the phase detector frequency in

自己顶一个

思考下，呵呵

从PFD的角度看，sigma delta modulator控制分频N或N+1，分频后的该信号在 PFD处 跟 参考时钟信号 比较，如果频率不一样，就失去了比较的意义。

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