12bit sar adc 500kps

自顶一下，有知道的请指点一下，谢谢了。

For the comparator: you should choose fully dynamic structure.
About the DAC: it's better if you use CDAC not integrate CDAC + RDAC.
There are a reference paper might be good for your selection:
"An Energy-Effi cient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C
DAC Structure" - JSSC 2014.

You should design SAR ADC with total dynamic comparator not static one to avoid large power consumption.
About using the CDAC or CDAC + RDAC, with 500 kS/s, I recommend you use CDAC.
This paper might be good reference for your selection:
"An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C
DAC Structure" - JSSC 2014.

顶一下。
打算用什么工艺? SAR ADC做12bit是不是比较难? 需要加校正吗?
500Ksps好像不是很高，就是做12bit精度比较难。
希望LZ多多交流，请前辈多多指教。

速度不高

能提供论文吧?

    谢谢！
我现在用的是三段式的CDAC，但在段与段之间跳变的时候总是有误差。
全动态比较器能否达到12bit?
我现在用的是静态比较器。有资料上说是10bit以下动态比较器，12bit以上是静态比较器，不知这个说法有没有根据?

   谢谢。
用的是IBM 0.18um工艺
正在想校正的事情，不加校正好像不行。

Hi mikeppq,
No one use static comparator for SAR ADC, because in SAR ADC, comparator involve in a lot of circles of switching, so static comparator can not meet the specification. To check this thing, you just design a static comparator with clock frequency (comp) = fs(SAR) * 12 (I assumed you design asynchronous SAR ADC), and probe the average power consumption.
Your ADC is design in 0.18 um, it's possible that supply voltage = 1.8v, so there are a lot types of dynamic comparator can stand for 12bit with this supply.
When you use 3 stages of CDAC, it means you will use split capacitor, right? if it's the case, the  problem is how you can do the layout for the bridge capacitor (example, Cb = 17/16 * Cunit).
The last thing is, if your design is for research, it's rare to see any papers had specification: 12b + sampling rate ~ 500kS/s. Normally, for biomedical devices: the res = 8-10b with sampling rate = 100k - 1M, and for wireless sensor network: res = 10-12b, fs = 1M-10M.

good one ！

谢谢共享

"An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C
DAC Structure" - JSSC 2014
请问是哪一期的?

500K SMPS， 12bit, 考虑null和sampling, 20个clcok周期就可以，clk 10MHZ，完全就用之前的
架构就可以了， 同步的SARADC， 12bit对电容和电阻match有一些要求，面积大一点，layout做好完全可以的。比机器最好静态的，有2级预运放，再到比较器。保证offset比较小。
   
      目前的最新的SARADC大都是asynchronous, 采样率10M~100M, 10bit精度以内的，这个难度比较大，但目前比较火。

速度不快，但是要加校准

啊啊啊！都这么强大

请问一下 如何将1LSB 的量化误差设计成±0.5LSB 呢，。是改电容阵 还是 给比较器增加失配

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