求教：关于流水线ADC的参考电压。

加大电容，或者reference buffer.
波动是正常的，只要不影响精度就好了

用folded cascode opa做buffer，就不波动了，在buffer输入前加电容滤波一下比较好

路过，搭车问：reference buffer的功耗会不会很大，在低电源电压下有没有较好的结构?

reference的功耗在整个adc里面应该不是最主要的吧，所以大小不是很关键。

pipeline最耗功耗的是opamp和SHA

不对吧? 如果没有片外电容，高速pipeline 的reference buffer 可是功耗大户，跟MDAC1不会差多少

pipeline
其实关于pipeline adc 参考电压设计一般有两种思路：一种是设计高速的buffer,不外加offchip cap;另一种就是可以用比较弱的buf，但是外加 offchip cap 来stable.高速pipeline adc 一般来说要用外加的cap 来稳定ref voltage;如果设计高速buf,buf 带宽就要很宽，响应速度才能很快，要在1/2 Tclk 里边稳定到需要的精度。对于100M 以上的这应该还是比较难的。

重新计算了一下，确实 我错了

1. Off-chip CAP solution
Advantage is low power, low nosie. But please remember since in this case, dominant pole is at OUTPUT, your buffer design must be careful. Your output impedance must be high, and all the internal stage impedance should be low to keep non-dorminat pole at high frequency. Otherwise there still stability issue. You can also refer LDO type design for this buffer. In the end, don't forget your ESD resistor may harm your performance

2. On-Chip Solution
Advantage is saving one PIN count. But as you may know, power is very consuming especially in hgih speed buffer. Also noise is another headache. There are many on-chip solution depending on your speed and resolution. I assume your resolution is 10bit and speed <200MSPS, OPEN LOOP solution is great help and simple and many many people like because no stability issue, simple circuti structure and more, power consumption is reasonable.
3. Final Suggestion
Remember,  reference buffer design is more difficult and important even than SHA. Don't take it for granted.
Hopefully it helps you.

谢谢大家！非常的感谢！

加大电容是那边的电容，参考电压的滤波电容吗?
reference buffer用普通的两级运放行吗?
同一个参考电压就只用一个reference buffer，比如+Vref过来,我就只接一个reference buffer然后接到每级的+Vref输入。这样行吗。
还是每级的+Vref输入都要接一个reference buffer。

我用普通的两级运放可以吗，还有一定要用folded cascode opa。

我就10bit 40M,或60M。我该怎么做，能指点一下吗。

thank you for your help.
i am poor in english. i cannot expression what i want to say  clearly. plsase forgive me！
i hope you can read chinese.
my design 10bit 40M or 60M。my boss is not  allow for another PIn ,so cannot use Off-chip CAP solution.
what do you think about the  opa buffer.
i am a new man. i hope you guide me .
thanks！

受益良多

学习了一下

学习了

10# prof3   niu , wanna learn more from you

pipeline adc 参考电压

唉，有啥问题直接问好了，不用太客气啦！
前面有几位说的都不错，buffer是个重要的模块，也可能是个功耗大户。
你想：在比较的时候，每隔一级的电容都要接在reference上，如果没有大的驱动能力，怎么给这么多电容充电?
所以，假如不用off-chip大电容的话，重要的buffer要有足够大的slew rate。如果采用classA，电流就大发了。
所以，可以采用class-AB结构，这样不愁slew rate了。还要看你的VDD电压够不够做个正常的class AB的，1.8V及以上应该够了吧！
buffer的带宽应该不算太难，也不会耗费很多功耗。因为就算是100MHz的采样率，buffer的GBW搞到200~300MHz也就够了。
有啥说的不对的，请指正啊！

受益良多啊

3x！

    什么是open loop solution?能讲详细点吗?

    甚至比MDAC1还大吧

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