首页 > 微波/射频 > RFIC设计学习交流 > Analog design signoff checklist

Analog design signoff checklist

录入:edatop.com    阅读:
Hello, can anybody share me analog design signoff checklist?
For example, in digital design, it will be
1. functional: test regression passing rate; coverage; etc...
2. Timing: STA; postsim; etc...
...
In analog field, in the real tape-out signoff flow, is there any similar checklist?
Thanks,

it's something you should already know before you became a manager

Can anybody share valuable experience here?

Thanks,

It seems a decent question, and it will help people to follow the right process.
There are two many people who are willing to take short cut, and very few people want to follow the process.

1. postsim at 5 corners and make sure there is some tolerance.
for example 300Mhz 10bit DAC spec, we have to postsim at  350Mhz or higher

Thanks, hugodarwin.
How many testcases do you use for simulation? Only some little sequences which can be put in one test case?

申明:网友回复良莠不齐,仅供参考。如需专业解答,请学习本站推出的微波射频专业培训课程

上一篇:怎样看cadence是哪一个版本
下一篇:IP如何仿真

射频和天线工程师培训课程详情>>

  网站地图