求助VERILOG-A的一个问题
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我在网上下了一个 NOR的VERILOG-A的模型
`include "disciplines.vams"
`include "constants.vams"
module V_nor(in,out);
input [0:size-1] in;
output out;
electrical in,out;
parameter real size = 2 from [2:inf),
vout_high = 5,
vout_low = 0 from (-inf:vout_high),
vth = 1.4,
tdelay = 5n from [0:inf),
trise = 1n from [0:inf),
tfall = 1n from [0:inf);
integer in_state[0:size-1];
integer out_state;
real vout;
interger i;
analog
begin
@(initial_step)
for(i=0;i<size;i=i+1) in_state=0;
generate i (0,size-1) //编译的时候说这句有问题 我不知道哪儿错了 然后我把这句屏蔽掉后 又说Array bounds for net 'in' must be constant in this .
begin
@(cross(V(in) - vth))
begin
in_state = V(in) > vth;
out_state = 0;
for (i=0;i<size;i=i+1)
if (in_state) out_state = 1;
if (out_state) vout = vout_low; // inversion of output
else vout = vout_high;
end
end
V(out) <+ transition(vout,tdelay,trise,tfall);
end
endmodule
请教下牛人 到底这个东西哪儿有问题了 或者给我发一个NOR的模型吧 我有急用 谢谢
`include "disciplines.vams"
`include "constants.vams"
module V_nor(in,out);
input [0:size-1] in;
output out;
electrical in,out;
parameter real size = 2 from [2:inf),
vout_high = 5,
vout_low = 0 from (-inf:vout_high),
vth = 1.4,
tdelay = 5n from [0:inf),
trise = 1n from [0:inf),
tfall = 1n from [0:inf);
integer in_state[0:size-1];
integer out_state;
real vout;
interger i;
analog
begin
@(initial_step)
for(i=0;i<size;i=i+1) in_state=0;
generate i (0,size-1) //编译的时候说这句有问题 我不知道哪儿错了 然后我把这句屏蔽掉后 又说Array bounds for net 'in' must be constant in this .
begin
@(cross(V(in) - vth))
begin
in_state = V(in) > vth;
out_state = 0;
for (i=0;i<size;i=i+1)
if (in_state) out_state = 1;
if (out_state) vout = vout_low; // inversion of output
else vout = vout_high;
end
end
V(out) <+ transition(vout,tdelay,trise,tfall);
end
endmodule
请教下牛人 到底这个东西哪儿有问题了 或者给我发一个NOR的模型吧 我有急用 谢谢
verilog-a 的i/o 不支持总线。
`include "discipline.h"
`include "constants.h"
//--------------------
// nor
//
// - nor gate
//
// vin1, vin2: [V,A]
// vout: [V,A]
//
// INSTANCE parameters
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for high [V]
// vtrans = voltages above this at input are considered high [V]
// tdel, trise, tfall = {usual}
//
module nor_gate(vin1, vin2, vout);
input vin1, vin2;
output vout;
electrical vin1, vin2, vout;
parameter real vlogic_high = 5;
parameter real vlogic_low = 0;
parameter real vtrans = 1.4;
parameter real tdel = 2u from [0:inf);
parameter real trise = 1u from (0:inf);
parameter real tfall = 1u from (0:inf);
real vout_val;
integer logic1, logic2;
analog begin
@ ( initial_step ) begin
if (vlogic_high < vlogic_low) begin
$display("Range specification error. vlogic_high = (%E) less than vlogic_low = (%E).\n", vlogic_high, vlogic_low );
$finish;
end
if (vtrans > vlogic_high || vtrans < vlogic_low) begin
$display("Inconsistent $threshold specification w/logic family.\n");
end
end
logic1 = V(vin1) > vtrans;
logic2 = V(vin2) > vtrans;
@ (cross(V(vin1) - vtrans, 1)) logic1 = 1;
@ (cross(V(vin1) - vtrans, -1)) logic1 = 0;
@ (cross(V(vin2) - vtrans, 1)) logic2 = 1;
@ (cross(V(vin2) - vtrans, -1)) logic2 = 0;
//
// define the logic function.
//
vout_val = (！(logic1 || logic2)) ? vlogic_high : vlogic_low;
V(vout) <+ transition( vout_val, tdel, trise, tfall);
end
endmodule
谢谢 楼上
都怎么找到这些例子的?
我用的IC DESIGN TOOLS里面有一些模型的 包括或非门的 还有其他的 像lpf vco等等
请问你用的是什么工具啊? 能不能把这些模型发上来 我现在正在学习这个东西建模
没有搞懂啊！
请教，verilog-a 不支持总线，如果前面是总线要做输入，在内部作控制，我该怎么办?
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