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pads9.3打开xilinx FPGA原理图出错
录入：edatop.com 点击：
00:00:00 Starting Migration
00:00:00 Project configuration files are being read...
00:00:00 CDB flow is not used. Migrate as NETLIST flow...
00:01:12 Migration stopped because WIR files may be out of date
00:00:00 Starting Migration
00:00:00 Project configuration files are being read...
00:00:00 CDB flow is not used. Migrate as NETLIST flow...
00:00:48 Migration stopped because WIR files may be out of date
ml50x_schematics.zip
00:00:00 Project configuration files are being read...
00:00:00 CDB flow is not used. Migrate as NETLIST flow...
00:01:12 Migration stopped because WIR files may be out of date
00:00:00 Starting Migration
00:00:00 Project configuration files are being read...
00:00:00 CDB flow is not used. Migrate as NETLIST flow...
00:00:48 Migration stopped because WIR files may be out of date
ml50x_schematics.zip
这个直接是打不开的要转换
如何转换请赐教！
用dxdesigner打开。
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