PADS 原理图倒pcb图

完整的错误信息是什么?
贴出来看看.

*PADS-ECO-V9.2-MILS*
*REMARK*old file: C:PADS Projectsppcbnet.asc
*REMARK*new file: C:PADS Projectspadsnet.asc
*REMARK*created by ECOGEN (Version 6.4v) on 2012/6/19 9:34:32
*DELPIN*
U33.19NSRAMA17
U33.20NSRAMA16
U7.A10NSRAMA17
U7.B10NSRAMA16
*CHGPART*
C130CAP0603@0603CAP0603@0402
C132CAP0603@0603CAP0603@0402
C136CAP0603@0603CAP0603@0402
*NET*
*SIGNAL*A_+3.3V
D2.1
*SIGNAL*A_VEDIOB_A
R20.2
*SIGNAL*A_VEDIOR_A
R22.2
*SIGNAL*FPGA_REST#
D2.2
*SIGNAL*NSRAMA16
U33.20U7.A10
*SIGNAL*NSRAMA17
U33.19U7.B10
*DELETE_GENERAL_RULES* HIGH_SPEED
HIERARCHY_OBJECT NET:NSRAM2_D3
*CREATE_GENERAL_RULES* HIGH_SPEED
HIERARCHY_OBJECT NET:NSRAMA9
HIERARCHY_OBJECT NET:NSRAMA8
HIERARCHY_OBJECT NET:NSRAMA7
HIERARCHY_OBJECT NET:NSRAMA6
HIERARCHY_OBJECT NET:NSRAMA5
HIERARCHY_OBJECT NET:NSRAMA4
HIERARCHY_OBJECT NET:NSRAMA3
HIERARCHY_OBJECT NET:NSRAMA2
HIERARCHY_OBJECT NET:NSRAMA19
HIERARCHY_OBJECT NET:NSRAMA18
HIERARCHY_OBJECT NET:NSRAMA17
HIERARCHY_OBJECT NET:NSRAMA16
HIERARCHY_OBJECT NET:NSRAMA15
HIERARCHY_OBJECT NET:NSRAMA14
HIERARCHY_OBJECT NET:NSRAMA13
HIERARCHY_OBJECT NET:NSRAMA12
HIERARCHY_OBJECT NET:NSRAMA11
HIERARCHY_OBJECT NET:NSRAMA10
HIERARCHY_OBJECT NET:NSRAMA1
HIERARCHY_OBJECT NET:NSRAMA0
MIN_LENGTH 0.000000
MAX_LENGTH 448000.000000
STUB_LENGTH 0.000000
PARALLEL_LENGTH 1000.000000
PARALLEL_GAP 200.000000
TANDEM_LENGTH 1000.000000
TANDEM_GAP 200.000000
MIN_DELAY 0.000000
MAX_DELAY 10.000000
MIN_CAPACITANCE 0.000000
MAX_CAPACITANCE 10.000000
MIN_IMPEDANCE 50.000000
MAX_IMPEDANCE 150.000000
SHIELD_NET OFF
SHIELD_GAP 200.000000
MATCH_LENGTH ON
MATCH_LENGTH_TOLERANCE 200.000000
AGGRESSOR OFF
*DELETE_GENERAL_RULES* HIGH_SPEED
HIERARCHY_OBJECT NET:NSRAMA16
HIERARCHY_OBJECT NET:NSRAMA17
*REMARK*Deleted pins: 4,Added pins: 8
*END*
这是完整的结果

*PADS-ECO-V9.2-MILS*
*REMARK*old file: C:PADS Projectsppcbnet.asc
*REMARK*new file: C:PADS Projectspadsnet.asc
*REMARK*created by ECOGEN (Version 6.4v) on 2012/6/19 9:34:32
*DELPIN*
U33.19NSRAMA17
U33.20NSRAMA16
U7.A10NSRAMA17
U7.B10NSRAMA16
*CHGPART*
C130CAP0603@0603CAP0603@0402
C132CAP0603@0603CAP0603@0402
C136CAP0603@0603CAP0603@0402
*NET*
*SIGNAL*A_+3.3V
D2.1
*SIGNAL*A_VEDIOB_A
R20.2
*SIGNAL*A_VEDIOR_A
R22.2
*SIGNAL*FPGA_REST#
D2.2
*SIGNAL*NSRAMA16
U33.20U7.A10
*SIGNAL*NSRAMA17
U33.19U7.B10
*DELETE_GENERAL_RULES*HIGH_SPEED
HIERARCHY_OBJECTNET:NSRAM2_D3
*CREATE_GENERAL_RULES*HIGH_SPEED
HIERARCHY_OBJECTNET:NSRAMA9
HIERARCHY_OBJECTNET:NSRAMA8
HIERARCHY_OBJECTNET:NSRAMA7
HIERARCHY_OBJECTNET:NSRAMA6
HIERARCHY_OBJECTNET:NSRAMA5
HIERARCHY_OBJECTNET:NSRAMA4
HIERARCHY_OBJECTNET:NSRAMA3
HIERARCHY_OBJECTNET:NSRAMA2
HIERARCHY_OBJECTNET:NSRAMA19
HIERARCHY_OBJECTNET:NSRAMA18
HIERARCHY_OBJECTNET:NSRAMA17
HIERARCHY_OBJECTNET:NSRAMA16
HIERARCHY_OBJECTNET:NSRAMA15
HIERARCHY_OBJECTNET:NSRAMA14
HIERARCHY_OBJECTNET:NSRAMA13
HIERARCHY_OBJECTNET:NSRAMA12
HIERARCHY_OBJECTNET:NSRAMA11
HIERARCHY_OBJECTNET:NSRAMA10
HIERARCHY_OBJECTNET:NSRAMA1
HIERARCHY_OBJECTNET:NSRAMA0
MIN_LENGTH0.000000
MAX_LENGTH448000.000000
STUB_LENGTH0.000000
PARALLEL_LENGTH1000.000000
PARALLEL_GAP200.000000
TANDEM_LENGTH1000.000000
TANDEM_GAP200.000000
MIN_DELAY0.000000
MAX_DELAY10.000000
MIN_CAPACITANCE0.000000
MAX_CAPACITANCE10.000000
MIN_IMPEDANCE50.000000
MAX_IMPEDANCE150.000000
SHIELD_NETOFF
SHIELD_GAP200.000000
MATCH_LENGTHON
MATCH_LENGTH_TOLERANCE200.000000
AGGRESSOROFF
*DELETE_GENERAL_RULES*HIGH_SPEED
HIERARCHY_OBJECTNET:NSRAMA16
HIERARCHY_OBJECTNET:NSRAMA17
*REMARK*Deleted pins: 4,Added pins: 8
*END*
这是完整的结果，这些报告具体是什么意思啊

这是ECO的更改信息吧，提示你原理图相对于PCB更新了那些东西。比如封装又0603改为0402，删除了某些网络，重新定义了那些网络等等。
保证你的原理图是对的就可以了，这只是提示你ECO 的那些内容，更新过去就可以了。如果你的原理图有错误，会有另外一个文件提示你原理图中存在的问题。