- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
PADS9.1即将催出
录入：edatop.com 点击：
9.02有很大BUG，所以mentor又匆匆修改了几个补丁，然后集合催出9.1，现在9.1已经进入最后测试：
pads 9.1 Customer Beta 6 已经出来：
PADS 9.1 Customer Beta 6
December 2009, Install 12587
Please submit defects for products as instructed below.
-----------------------------------------------------------------------------------------
Defects for PADS Layout, Logic, Router and DxDesigner should be submitted to the Beta products on SupportNet,
which are BETA_PADS_Layout, BETA_PADS_Router, BETA_PADS_LOGIC and Beta_PADS_DxDesigner.
***IMPORTANT*** - Known Issues and Future Changes
-------------------------------------------------
1. DxDesigner and related programs from EE2007.8 are now included in this release.
2. Archiver functionality is now available in the Tools menu of Layout, Logic and Router as well as DxDesigner.
3. During installation there is an error with the post install script "accuparts_dx_postinstall.bat".
See the reference notes below for a list of functional updates and current fixes.
Regards,
The PADS Beta Team
Setup, Licensing, Installation, and Distribution
------------------------------------------------
- Windows XP and Windows Vista Japanese are supported.
- Database formats for Layout, Logic and Router designs have changed.
- You are required to have a licenses file with an exact access date of November 1, 2009 or later to run this release.To determine the Exact Access Date (EAD) of your license file go to mentor support net。
PADS9.1 is a completely separate installation from previous PADS releases, The Installation
path for PADS9.1 is now C:MentorGraphics9.1PADS.While PADS9.1 does not overwrite
previous PADS installations, you should back up your existing PADS installation, designs and
libraries prior to installing PADS9.1.
Fixes/enhancements for HyperLynx Thermal
----------------------------------------
none
Fixes/enhancements for HyperLynx Analog
---------------------------------------
dts0100634577Apex Engine doesn't complete simulation for Digital Models
dts0100636111Infohub Help & Manual Scope incorrectly says "Analysis - Simulation and Signal Integrity with HyperLynx Analog
dts0100634078Eldo MC78xx models are incorrect and do not simulate correctly
dts0100636035The SPICE model libraries do not load when useing Eldo with PADS
dts0100608146Exclude Component not shown in Japanese menu
dts0100608582[Simulation Control dialog] :"DC Sweep Parameters" page --> "Add' doesn't behave correctly.
dts0100616119.option tuning will override user value for eps
dts0100631676Incorrect netlist from distribution dialog
dts0100608021Exclusion should work hierarchically
dts0100614981Eldo behaves different than the other netlist formats
dts0100615983The VHDL Netlister should handle the (Read-in output) by creating an intermediate signal
dts0100615994Wrong netlist when symbol pin number is greater than model port number
dts0100618238VHDL netlister does not handle ports properly
dts0100620878Wrong VHDL code with component array
dts0100622857[Netlister] Netlist error in ports connection with buses
dts0100630659[Netlister] VHDL netlist generated for the attached project is incorrect
dts0100632875[Netlister] Output port is not mapped correctly to the bus connected to it
dts0100632876[Netlister] When Port name is same as bus name, the buffer name will be incorrect
dts0100633267When switching simulator between ELDO and HLA, dxnetlister.ini lost [SpiceHeader] information
Fixes/enhancements for HyperLynx
--------------------------------
dts0100629862HyperLynx BoardSIM export from PADS Layout places plane areas within signal net definition
Fixes/Enhancements for PADS 3D Viewing (Note: 3D Viewer 2.0 is included in PADS 9.1)
------------------------------------------------------------------------------------
dts0100605690Layer 20 (footprint courtyard) is used when generating the 3D view.This causes problems with the new 3D viewer
dts0100635846Component heights are incorrect
Fixes/enhancements for PADS Layout
----------------------------------
dts0100592339Netlist from DxD is wrongly loaded into Layout if Unit attribute in DxD is set to Metric.
dts0100621636PADSLayout hangs when you want to substitutes part with Decal that has 'increaded Layer mode'
dts0100601402Time stamp for Part Type on pcb design is not updated when you modify attributes.
dts0100631451Change label in HYP Export dialog box
dts0100544158Poor outline information sent to 3D Viewer - Beta 3
dts0100547218Gerber preview shows short in the design. But there is no errors if we run clearance check.
dts0100593049PADSPCB_Decal Wizard - RMB opens main window popup if cursor is over a data line or title line (Defect for 9.1)
dts0100593100PADSPCB_Decal Wizard - Default layers for outlines in the decal wizard options should be Silkscreen Top, Assembly Top and Layer_20
dts0100593106PADSPCB_Decal Wizard - Selection pop-up on cells is appearing in the grid controls of decal wizard and decal wizard options dialogs.
dts0100593107PADSPCB_Decal Wizard - Decal Wizard: Create crosshair as two "L"'s (instead of two crossing segments).
dts0100593110PADSPCB_Decal Wizard - Decal Wizard dialog: Default button should put some values for component dimensions in the "Land Pattern Calculator" group.
dts0100622131Pads definition on solder mask is incorect for through hole device type generated by IPC decal wizard
dts0100622230Incorect dimention name in the grid
dts0100622475Placement outline is shifted for generated decal
dts0100622697Preview window displays colors incorectly
dts0100623701Notch for assembly outline should have separate control checkbox
dts0100623736Rounded corner radius is incorect for pads on solder and paste layers if mask expansion is used
dts0100623783Generated decal is collapsed for those specific parameters
dts0100623797Tab order works incorectly for wizard dialog
dts0100624535False pad to pad clearance error is indicated
dts0100628883Distance between pads and silkscreen is incorrect for quad decal
dts0100629011Some pads are not rotated for Polar decal
dts0100629304Preview window blinks after pressing default button in BGA tab
dts0100632350Units groups in the decal wizard and wizard options dialogs are NOT in synch with unit setting in the Tools->Options dialog
dts0100633384When a configuration file is missing used gets a misinforming message
dts0100629345Polar tab does not respect the silkscreen line width parameter
dts0100582679When the "Remove unused pads" feature is used, pads within "copper pour and plane area" keepouts are not removed.
dts0100620173Runtime error while doing Forward to PCB.
dts0100634090Runtime error viewdrawlink on update PCB
dts0100472613Not possible to change parttype with PCB-Decals with different number of terminals
dts0100480393Pour Manager does not consider board - Copper Clearance Rules
dts0100570786Bad flood data creates short across 4 nets which Verify Design did not catch
dts0100605615Boldface not used correctly on "PADS Layout GUI Reference> Options Dialog Box, Grids Tab" help page
dts0100633511Change the help menu item to point to a different book
dts0100632059Altium Designer 2006 file will translate in V2005 translator but crashes at 75% in V9.0.2 translator
dts0100593860DXF and IPC export generate Fatal error occurred while exporting design - operation aborted
dts0100473144Length minimize during move will not work when connection is established to partial route or via.
dts0100629626MACRO - When I run the attached macros, the result dialog box doesn't appear. In previous versions a window would popup listing the number of errors found.
dts0100627987When modeless commond "zc" is used, PADSLayout is freezing.
dts0100633930Too crashes when we export ODB++ for preview.pcb
dts0100636557ODB++ Output error (Fatal error: layer -1 not exported！)
dts0100527420Tool allows to create 'Thermals' for SMD Test Points, which leads to series of issues.
dts0100630528Create PDF - Graphical error in copper (Beta 3)
dts0100631593Create PDF - Some Ref Des are rotated (Beta 3)
dts0100631669In PDF User defined Untipads are not added on CAM Plane layer
dts0100631920Create PDF - Remove Bookmarks for components not included in PDF file(Beta 3)
dts0100635884Creat PDF process request hundred times for component that does not exist in library
dts0100496801Reuse Copy loses Flood Priority, resets all to 0
dts0100419975Remove unused pad does not work for nested planes where the outer plane net was used in the inner planes
dts0100636198Crash when removing via from routing via list
dts0100637331Pads disappear when zooming in/out
dts0100635066"Fatal Data Base Error Number 2012" and crash during opening a design in non licensed mode
dts0100600676Picture and information about UFL dialog window should be updated in FSP (or implementation should be changed)
dts0100621629Strange message appears when you perform UFL in Layout.
dts0100634588Update From Library creates Undo Checkpoint even if no changes are made in the PCB Database
dts0100634589UFL dialog: Remove Selected Items button should be ghosted when no design items are selected.
dts0100634608When you import an ASCII file netlist into a new pcb database the decal and part timestamps are not included.
dts0100634609"B.The part type section contains 6 parts that show ?Different? in the? Content column ?but only one of the six has a value in column ?see line?. Should have a line number on all 6of the items that sh..."
dts0100634613The "see line" of Part LITTLEFUSE-V18AUML2220(located at line 89) shows 195 in the "see line" column but it actually starts on line 193.
dts0100634615Timestamp values are not shown in the Part Type Summary.
dts0100634616Line 136 should not truncate names. Wrap the text to the next line or show the entire value.
dts0100634620"C.Line 644 states the Attributes in the library are 16 and the attributes in the pcb are 18. The actual decal has 18 attributes looking at the actual decal in the library file lenny.d"
dts0100634622"F.Looking at line 682 685 686 the counts are equal yet the comparison field shows not equal. Each of these should have additional lines underneath them showing the actual item that does not compare. ..."
dts0100634637"Looking at REPORT-LIB-UPD-ALL.TXT contains the following errors. (Generated from PCB File LIB-UPD.PCB). e.Line 11221, 11336 states they are not equal yet the 4 lines below that are equal."
dts0100634646Even if you update all the parts using the library update to update them there are still errors when comparing the library to the pcb. Please see REPORT-PARTS-UPD.TXT
dts0100637697Parttype timestamp in PADS Layout is not correct if "Send Netlist" is used - (Beta 5) Could be related to dts0100634641.
Fixes/Enhancements for Logic
----------------------------
dts0100623556Component attributes with a value can not be emptied in Edit Part.
dts0100629839Global switch in options to turn on/off place holder attributes in Logic.
dts0100591808Update Logic Sample Files
dts0100428973ECO/Compare reports No Differences Found when one of the files is read only-should indicate it needs write permission
dts01005929010906021756_PADS_LogicCrashReport
dts0100533663Deleting vias in Via Definition > Via Setup does not work
dts0100630556Autotest detected: "PIN Decals" instead of "Pin Decals" in Update from Library dialog box
dts0100623987Fatal run-time error
dts0100579379Automation method ExportNetList wasn't modified when the number of items to select had increased
dts0100619394Regression: If you edit a part from the schematic and add an attribute the attribute is not included after returning to the schematic
dts0100614860Getting error message 'Fatal Runtime Error' when I try to generate File > Report > Unused
dts0100349358Adding Classes with spaces crashes Logic
dts0100574637More than one net is unknowingly selected in the rules after performing a specific set of steps.
dts0100537702There should be a Select list for each Item. Right now, only the Pin Decal has an individually selectable list.
dts0100537705"Update from Library" should be on context menu when selecting a part or parts.
dts0100552427UpdateFromLibrary cannot handle same part types with different attribute values (in report)
dts0100571175UpdateReport detects hierarchical sheets as CAE-Decals - Beta 9
dts0100579630Alternate PCB-Decals still produces false differences in UpdateReport - Beta 11
dts0100593092PADSLogic_Update from Library - ENH:indicate library name in the report (for library decals, parts)
dts0100618873Header in PADSLogic UFL report should be updated.
Fixes/Enhancements for Router
-----------------------------
dts0100628438Saving file in pads router causes fatal error.
dts0100450331Why can't Blazeroute.ini be populated with the new options in their default conditions, so users don't need to type everything in?
dts0100531461Incorrect parameters in Router
dts0100583129Crash dump
dts0100635895Design verification scheme list not work correctly.
dts0100493262Default Windows dialog is displayed for some controls
dts0100634385Library Not Registered errors when PADS is installed to a directory with spaces
Fixes/Enhancements for Install
------------------------------
dts0100498605Need improved handling of the "lost license" scenario in PADS
dts0100569313PADS "Hardware Key Utility" program to make testing keys and installing/removing drivers much easier for customers
dts0100621527While installing the program got error message "C:MentorGraphics9.1PADSSDD_HOMEcommonwin32libMGCLibDataGrid.ocx" failed to load for Registration.
Fixes/Enhancements for IO Designer
----------------------------------
dts0100635950Layout form Allegor is display incorectly.
dts0100635963Missing brd and hyp filter of types in select path to layout.
dts0100637587IOD display only current fpga on device view (Layout import form allegro).
dts0100638335cadence IOD8.2: Got 'Unknown flow！' error message when trying to import schematic design.
dts0100602206IOD not outputting good Actel PDC file
dts0100633957Wrong recognize diff signal form QSF file
dts0100625917After import QSF some differential signal are doubled
dts0100625992It's impossible to import properly diff signals from pin file if it's use '(n)' convenction of naming diff pairs.
dts0100616628'configurator -uninstall' didn't remove IOD entry from menu start
dts0100621897Poor support for IOD installed as single product.
dts0100630357EE 8.2: Installting IOD 8.2 alone would not register the product on Windows.
dts0100616905IOD does not dump tcl command while import signals from spreadsheet is performed.
dts0100636590Iod deleted all project files.
dts0100629434IOD is not responding for over 13 minutes after selecting GND signal.
dts0100633035Cross probing :highlighted wrong signal in IOD while selectingnet in DxD
dts0100625292Pin swaps are not imported
dts0100616652IOD hangs after minimize die size is run in specific case.
dts0100615802Documentation for IOD8.1 should be improve.
dts0100632600Documentation incorrect in regard to Symbol Wizard.
dts0100614543Write to Local PDB file is not remembered
dts0100617368PADS9.0.2 The builtin 'symbi.1' cannot be exported. The path doesnot exist.
dts0100619265PKG_TYPE and SIGNAL attributes are not exported to ICE in pads flow
dts0100619614Differential buses are not connected on the IOD generated schematic.
dts0100630977Remove design doesn't work.
dts0100632139EE IOD8.2: IOD showed a fatal error when running run.tcl.
dts0100636406EE IOD8.2: IOD crashed after export_all_schematics command was issued.
dts0100625329Importing assignment for diff signals from dxd project does not work
dts0100632195Schematic Update is removing and not adding any power, ground and/or config pins defined as signals and/or added to the PCB symbols in the DxD schematic.
dts0100615847NSE seemed to crash on the 'exit' TCL command on Linux only.
dts0100617458De-scoped I/O Designer for PADS Suite
dts0100620002ANALOGVCC is migrated incorrectly
dts0100620440Inconsistent behaviour in creating differential signal name
dts0100624825Spread functionality of Types Compatibility options for HDL signals
dts0100624857"Project could not be saved" because design name has space character.
dts0100626736Environment variable in .prj file not supported
dts0100632352Llicense dialog - empty license options in 'PADS I/O Designer'
dts0100633373SSO value is calculated wrong for differential signals.
dts0100635946Migration of old database should be improved.
dts0100620449Duplicated signals after importing from HDL and QSF
dts0100636022Crash of IOD while importing vhdl entity.
dts0100616013Wrong HDL created/exported
dts0100617953Space character in design name makes problem for IOD.Error: Top level must be set.
dts0100633055Import PCB Design Wizard: Whole signal is unassigned when one pin type is not compatible with signal type
dts0100597469[BSXE] Importing swap in lpc database results in broken connectivity if component database is not synchronized before
dts0100616740Background on Layout view is always black on Vista 64
dts0100621328Unravel on my design with diff signals causes error messages during applying scenario
dts0100630751Library parser failure while importing schematic into layout database.
dts0100633294Partition name is not displayed on Layout Setup window
dts0100633924Signal names disappear on connectivity window after importing pcb layout
dts0100615858IOD8.1: IOD crashed on the TCL file.
dts0100616812IOD8.1: TCL command, exportsymbol, resulted in an error.
dts0100618901Improving TCL script recorder
dts0100623194IOD8.1: TCL command selectsignals A caused IOD to crash.
dts0100631902License dialog is empty on linux after running IOD (refresh problem)
dts0100632077EE IOD8.2: Available license options were not shown for the full version IOD.
dts0100632627Some option related to die database are redundantly displayed in Tools menu for other databases.
dts0100633752EE IOD8.2: IOD crashed on running the TCL file on Linux
dts0100634470EE IOD8.2: IOD crashed when I tried to use TCL commands to select signals after running a Dx VBS script.
dts0100635370EE IOD8.2: IOD crashed with C++ Runtime Library error when adding a new FPGA design.
dts0100638815IOD crashes while openning customer's database on Linux.
dts0100597062Export to AIF from package dbis not required after applying swap on layout db
dts0100607448Import package cell preserving assignments where possible
dts0100628060Error message after reimporting cell into package database with diff signals
dts0100629676Unassign all => cannot unassign signal 'diff_test' - signal diff_test doesn't exist
dts0100605036Types Compatybility does not support an assignment exception
dts0100619916There is no possibility to assign differential signal to pins 8 and 9 in Altera's device.
dts0100624059IOD is not responding while assigning pcb signal with Shift pressed.
dts0100632373Error while importNetlist file (Spreadsheet): .csv, when signal type charakter are small
dts0100632383No assing differential signal (but no DIFF type) afterImport Netlist Spreadsheet file: .csv
dts0100632619Cannot assign output IO signal
dts0100623389'View pins from other devices' doesn't show common pins. Pins list is empty.
dts0100635506IOD is repositioning windows constantly depending on cursor position what looks like IOD is blinking.
dts0100621902Database Settings not prompted when loading FPC.
dts0100631933Creating net-list project ends with error
dts0100633129EE IOD8.2: Got an error on Linux: vmwlm: [11:14:40] error VMWLM0301: License server not found.
dts0100633480EE IOD8.2: IOD failed to create a new project on Solaris.
dts0100626020Rule engine operators have incorrect English
dts0100635228Input pad with INPUT TERMINATION has to be at least 1 LAB away from differential pad.
dts0100635867Rule: Single-ended output and differential signals assignment" work unproperly.
dts0100619597Unplaced tab improperly shows connectivity problems in some case.
dts0100619601Symbol Wizard does not place all signals on PCB symbols in specific case.
dts0100619941Wrong information of selected differential signals.
dts0100620427Corrupted database structure
dts0100619606After splitting bus signals symbols become broken.
dts0100619852It is not possible to exit from mode of adding items (like arc, circle) with ESC key.
dts0100632577IOD writes to transcript some redundant information while symbol edition.
dts0100618530IOD crashes after manipulating signals in the last step of symbol wizard.
dts0100619946Symbol wizard doen't generate symbols with differential signals in specific case. Refresh problem.
dts0100619965'create bank power symbols' is not set up after rerunning symbol wizard.
dts0100626048Sym Wizard assigning incorrect power signals to pins.
dts0100628170Broken PCB symbols after updating.
dts0100629352Symbol Wizard settings 'split only pcb symbols' were not stored in fpc.
dts0100632906Design tool selection dialog is redundant because it is determined before project creation.
dts0100635477IOD crashes while Symbol Wizard performs symbol update
dts0100548702Synchronization wizard in relation to Export cell from die should be corrected.
dts0100596151Synchronization needs to be less sensible. Moving non-IOD symbol shouldn't request import necessity etc.
dts0100599155[Synch. wizard]Export Connectivity table is not available on Synch. Wizard
dts0100606842Everything is matched, however SW indicates, that synchronization is needed.
dts0100614895Gray synchronization indicator sometimes blinks
dts0100617886IOD does not request updating symbols after unraveling (some assigned pins are not placed on PCB symbols)
dts0100617937Synchronization bubbles are yellow while no tracked file export/import is needed.
dts0100619881"Document needs import " during exporting schematic for all components
dts0100624493[Synch. Wizard] Tracking check box does not work properly on Files View for DCDV files
dts0100628627Incorrect export sequence: CES and schematic, but should be opposite. Lost constraints.
dts0100628925[Synch. Wizard] Connectivity Table checkbox is sorted and causes CES disappears
dts0100631718[Synch. Wizard]Import schematic is not required on new layout database
dts0100632062Synchronization wizard contains not added files just after creation fpga database
dts0100633995Lack of 'update graphics' in Synch. Wizard for Schematic Design import.
dts0100635491Import schematic is not requested in synchronization wizard after it is packaged (refdes changed)
dts0100620177Poor results of unraveling for attached testcase.
dts0100629113Unravel of crossover nets is broken.Immediate fix needed.
dts0100631688Unravel on layout database does not work
dts0100491672IOD crashes with PROLOG SYSTEM ERROR when unraveling nets in device view
dts0100636192Broken connectivity in Device View - Synchronization Wizard suggest no action. Database corrupted.
dts0100632012Incorrect warning message during export to UCF file.
dts0100633340Change default bus brackets for Xilinx UCF.
dts0100614926Please add support for ISE 11.2 library.
dts0100616172IOD needs to support the Spartan 6 devices.
dts0100368440IO standard has not been removed from ucf.
dts0100622444Redundant signal is imported from ucf: mcb3_dram_dq.
dts0100622447IOD should not remove from ucf: TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"2.5ns HIGH 50 %;
Fixes/Enhancements for DxDesigner from EE2007.8
-----------------------------------------------
dts0100586982ict viewer has a menu pick for slice and dice, but no documentation for this function.
dts0100566586Icon for deisgn path for additional symbol translation in Translation result dialogis wrong
dts0100567745Cadstar pin types are translated incorectly
dts0100592920CCZ output: Text has wrong orientation in CCZ file for symbols that have been rotated 180 degs or flipped
dts0100633799Verify: drc-201 reports an error when there is none.
dts0100595040Diffpair Restrict Layer Changes does not BA by existing ECO file
dts0100619515It is impossible perform BA using DxDesignerLink
dts0100633269DxArchiver is completely not usable for big designs
dts0100627152The selected component pin object can't be got.
dts0100636979DxDesigner crashes when quit command is invoked and DxDiagnostics is running
dts0100637220DxDesigner crushed when attribute is added by Automation Comp.AddOats / Comp.AddAttribute.
dts0100631832Launching Dx resulted in an error of missing prop_reuse_gui.vbs.
dts0100626155While crossprobing pins in Expedition, DxD crash. Scott was in DxD as well in the page that was being crossprobed to at the time.
dts0100631134Documentation incorrectly refers users to circle object if they want to create an ellipse
dts0100614450Live Verify fails when using the option "Use symbol data from Central Library".This appears to be a regression from EE2007.6.
dts0100614912ListBoxes to create query on dxdb grid display always all values from specific column during query creation.
dts0100615165Japanese menu problem: In the pull-down which selects the slot of DxDB, displays of "Slot" translated into Japanese are not all displayed.
dts0100616337"Part Number: invalid identifier" error during verification with oracle database when "Use symbol data from Central Library" option is set.
dts0100616340"Query is too complex" error during verification with some central libraries and "Use symbol data from Central Library" option set.
dts0100616953Closing and opening DxDataBook may cause disappearing icons on CL view tab.
dts0100616993"Query", "Criteria" and "！" buttons are disabled after loading component.
dts0100617241Export symbol(s) works differently if run from DxDataBook pop-up menu and NSE File menu option
dts0100617992There is a error after selecting tables joined horizontally.
dts0100618179When placing components from DxDatabook it don not change "," comma to a "." dot as it do in 9.0PADS, this result in error when doing netlist.
dts0100629771The query can not be created on the grid after selectinglibrary.
dts0100629777The verification buttons in databook can be enabled with Interconnectivity Table in one case and it can cause errors.
dts0100632306In a Netlist Flow Project we cannot Select multiple Symbols in Symbol Tab of CL view of DxDataBook
dts0100632348A message error is displayed during query creation on the grid for ALL library in some conditions.
dts0100632402"Clear the Current Search" option does not clear a grid displayed forlibrary.
dts0100632407Button 'Enter user / password' is truncated on Japanese WinXP
dts0100632412"Remove Condition" does not work inlibrary.
dts0100632708Verification in DxDatabook crashes viewdraw(regression to 2007.7)
dts0100634366Crash library wizard during creating horizontal table for expedition flow.
dts0100637275Crash during hierarchical verification on specific project.
dts0100372438DxPDF EXP2005.1 generates smal dots instaed of text on Solaris 8 and 9
dts0100541964DxPDF pager order does not work based on the scout SHEET order property.Please reference DR 541962.
dts0100631034DxPDF crashes if "Schematic Sheet Order Property" is used
dts0100633031Please correct the message'Genration ICTs to PDF document (with conversion ICTs to schematics).'
dts0100602277Pin number will not be displayed if Pin Label are either lower or mix case.
dts0100603902"Add Missing ports" on an IO Designer generated schematic for DxDesigner the ports are placed outside the schematics.
dts0100608356Cannot read correct coordinates of scaled symbols in DxDesigner
dts0100611157Part View place with slot fails with lowercase pin names
dts0100615128In the "Find and Replace Text"dialog, the "Select properties only" option is not translated into Japanese.
dts0100615499Japanese menu problem: "Select object > RMB > Pop-up menu" dialog has some issues of a Japanese translation.
dts0100616656Problem with move schematic
dts0100616682Multiple Signal properties are lost when importing ExpeditionPCB netlist design to ExpeditionPCB iCDB integrated flow
dts0100616955Symbol is not updated on schematic when editing it in NSE
dts0100617637DxDesigner must support metric symbol format
dts0100618285Properties addin does not show a name of a net ripped from a bus.
dts0100619905Clear Backups should be inactive for a read only schematic.
dts0100619942iCDB error when placing an updated symbol
dts0100620246Escape does not apply to Rip Net command
dts0100621606Update bus signals removes one of the bus names
dts0100621892unnamed bus segment created after renaming a bus
dts0100622476Push Schematic does not reflect sheet order
dts0100622848DxD Diagnostics reports invalid net errors after moving a component
dts0100623038It si not possible to add ICE Reuse Block to schematic
dts0100623061Enhance Add Properties Dialog
dts0100623427[Linux, Solaris]Show Strokes option doesn't work properly
dts0100624036'DxDesigner application has encountered a problem and needs to close' is not closed when restart is chosen.
dts0100624188add special component; [esc] does not work
dts0100624193Change the message issued when a user types an illegal regular expression
dts0100624578Endless bus created when connecting to an off grid component
dts0100624782Symbol of the array component contains block name.
dts0100624866Invalid global net created
dts0100624886DxDesigner diagnostics fails to correct errors in an imported design.
dts0100626698While crossprobing in CES, DxD crash.
dts0100628557viewdraw crashes when there is no write access to WDIR
dts0100628735Error 1287 when trying to delete bus segment. Diagnostics results in schematic that cannot be opened in schematic or block view.
dts0100628911Modify delete sheet message when this option is chosen from the Navigator
dts0100629037'Error 1287: iCDB database update error: Invalid parameter' when updating bus signals
dts0100629072Select all symbols on a sheet and deleting the Ref Designator property values, wrongly adds Ref Designator property to symbols that didn't have it previously.
dts0100629389DX2PADS changed interface - update in DxDesigner is needed.
dts0100629746DxDesigner Diagnostics large memory allocation on this testcase
dts0100629772Buses and bus rippers disassociation when moving a circuitry around
dts0100629789Connectivity errors in a design created from the scratch.
dts0100630095Shorted nets after renaming a bus
dts0100630174[Linux] DxDesigner crash when I press Undo
dts0100630197Diagnostics error after changing bus ripper connection using 'Net is being connected to bus' dialog.
dts0100630199I get Commit iCDB database transaction rejected. Reloading project when I choose rollback
dts0100630678Wrong connection with GND and diagnostic errors after schematic modification
dts0100630683I get GPF when I press Undo
dts0100630691Incorrect global net name after merging two nets
dts0100630706Wrong connection has been created after updating bus signals in the project
dts0100630958"Push to schematic" does not work after using "extract schematic" during placing new block (regression to 2007.8.12157)
dts0100630973Problem with DxDataBook window when I change expedition project in to netlist
dts0100631052viewdraw crashes when in a text being added to the schematic Unix like end of line characters are used (0A)
dts0100631270I got error: "Can't open symbol definition for schematic block！"
dts0100631630I get Error: Schematic block 'Schematic1.1' has elements with duplicate IDs needed for Backup/Rollback and copying
dts0100631663Renaming a hierarchical connector connected to a global net might create an invalid global net.
dts0100631721Navigator shows incorrect connections for hierarchical bus bundles
dts0100631730Placing a composite with Add Nets and Add Net Names adds a net for a pin using bus bundle name.
dts0100631935iCDB transaction rejected - project was reloaded when three users were pasting sheets at the same time
dts0100631973I get GPF when I choose Undo option
dts0100632623New Project dialog -> Advanced does not set paths to the cns and cfg files.
dts0100632639Rollback option does not work properly
dts0100632669Rollback not save correct design state after backup fixed by DxDiagnostic schematic
dts0100632681"Commit iCDB database transaction rejected" and eventually DxDesigner hangs when running packager and pasting sheet at the same time
dts0100632963[Concurrent mode] DxDesigner crashed when first user was deleting some sheets and other user attempted to delete one sheet right after he opened the design
dts0100633301Cannot package design just after migration - regression
dts0100633970DxD Diagnostics reports connectivity errors after undoing nets renaming
dts0100634006viewdraw crashes when exporting connectivity from ICT
dts0100634010When viewdraw is restarted automatically via the crash handler ('Restart the application and open the recent project') it consumes 100% CPU and is unusable
dts0100634021I get GPF when I choose Flip for ripper symbol
dts0100634256crash dialog has some issues on Windows XP Japanese
dts0100634305Issues with a DxD Diagnostics 'Test: Top Level Name Consistency'
dts0100634332Incorrect connections detected by DxD Diagnostics after copy-paste a schematic sheet
dts0100634819I get DxDesigner is Offline mode when I connect symbol with nets
dts0100635233DxD Diagnostics fails to fix 'Top Level Name Consistency' error in one pass
dts0100635581DxDesigner crashed after nets deletion
dts0100635605I get GPF when I choose Mirror option
dts0100635619I get GPF when I choose Flip option
dts0100635865I get Error 1287: iCDB database update error: when I press Undo
dts0100635936Problem with connection when I change size for bus
dts0100635972viewdraw crashes when flipping a bus ripper
dts0100636130Japanese menu problem: RMB popup menu of component and Block.
dts0100636316Propagate Properties Hierarchically locks all the project sheets (locks remains after it finishes)
dts0100636336During copy paste scenario, creating new sheet creates it in the wrong schematic.
dts0100636675I get Error 1287: iCDB database update error when I press Undo
dts0100569325Copy sheet does not copy block hierarchy when copying constraints is turned off
dts0100626105DxDesigner does not undo and error message Error 1296: Duplicate IDs detected
dts0100635209New DxDesigner Crash Catcher Dialog Details button should be removed
dts0100634336DxD crashes after replace when ODBC(Text, CSV) alias doesn't exists.
dts0100605359HDL: the Unmap option sends vdel command
dts0100608880HDL: Add zoom in/zoom out options to zoom inside the Waveform window
dts0100615226Migrration on design with $ARRAY attribute stops without clear message what is wrong
dts0100615987HDL: waveform stops displaying values after 100 ns
dts0100617492Using Builtin ports IN and OUT in schematic gets reversed in the generated VHDL code
dts0100617927HDL: the HDL Target Library for HDL Design can be set as the Modelsim system library
dts0100620510HDL: cannot simulate configuration for attached design
dts0100621591HDL Simulation settings. ModelSim executable file should explicitely mention vsim.exe
dts0100621605HDL: the path to the external text editor is truncated when it contains space
dts0100621903Cumbersome handling of leaf components
dts0100622290External Dx-ModelSim Flow: Unable to backannotate sim values into schematic
dts0100625569HDL: problem with the path to hdl file attached to component
dts0100625915Crash when setting the Modelsim executable folder
dts0100627635Setting notepad++ as external text editor and then changing it causes runtime error
dts0100627645Changing the default external text editor has no affect until DxDesigner is restarted
dts0100630111Library is not shown in the HDL Libraries window when it has name with dash "-"
dts0100630591HDL: signal names with signs , -, + and space are wrongly exported to vhdl/verilog
dts0100631341Inclomplete simulation macro for Modelsim
dts0100633001HDL files are duplicated in the Project Navigator - regression
dts0100634318Cannot set simulation top level when using ModelSim 6.3a SE as internal simulator
dts0100635137The HDL Search Paths entries are doubled each time I export vhd/verilog netlist
dts0100635583Viewdraw crashes when editing hdl file, but the path to the external text editor is not filled
dts0100629187DxDesigner Diagnostics does not fix the attached project.
dts0100632498MGC_REMAP_RSCM does not work with server:port format
dts0100620443I get Error: (521) [Block fghf] Cannot change interface of symbol placed on schematic when I delete for block or net
dts0100625205Reference designators for elements from fub in ICT, project explorer and Properties window are displayed incorrectly (U? R?)
dts0100629327Constraints are lost after rollback in ICE based design
dts0100629380File->Rollback removes a design from Navigator tree
dts0100631286Symbol Update -> Clear All Highlights does not seem to work in ICE documents
dts0100631297RMB menu 'Symbol Update' does not work in ICE based netlist projects
dts0100631302It is possible edit Read Only RB in ICE
dts0100592947DA2DX did not rename the Supply Rename value
dts0100593885DXD can not package if a hierarical symbol have vector pins nd the internal sheets have single ports for buss pins
dts0100600087few DA hierarchal blocks are translated into Blocks but not into Designs level
dts0100596003DC2DA and DxDesigner need to support LineStyle6-LineStyle16 from Design Capture.
dts0100630918"Unable to open Central LIbrary" error message with the "Create local DxD symbols from DC schematic" option enabled
dts0100631073Translation from DC to DXD causes Duplicate IDs that cannot be repaired using DxDesigner Diagnostics
dts0100615611Orcad Schematic to DxDesigner 2007.5 Translator should have the option to set all colors to "automatic"
dts0100622712The customer has an Orcad Capture schematic, which he converted to DxD. The schematics look fine, but when he generates the netlist and opens PADS Layout he finds a wrong connection (short-circuit).
dts0100624063Pin types migrated incorectly
dts0100625630Unexpected fatal error occured when there is no path to file in Browse frame
dts0100632606Specified file is corrupted or incorrect after import ffs file into DxDesigner using LineSimLink
dts0100633786Incorrect documentation - Importing from HyperLynx with LineSimLink
dts0100619566Export ccz - rotated properties are incorrectly exported
dts0100619652DxD Packager dialog has incorrect text
dts0100622705Solaris - File->Export->Analog netlist does not work
dts0100624832[Linux] Viewdraw crashes after Replace part when data source is ODBC compatible.
dts0100624912Add hierarchical property propagation script to the install
dts0100625050Schematic sheet cannot be opened after updating EE2007.3 project to EE2007.5, EE2007.6 OR EE2007.7
dts0100626477[i]/2007.8EE/docs/data/DxWDIR.zip design not working
dts0100626672pdbslot crashes DxDesigner
dts0100627156IOD cannot create Design. vipc: Error 1347: Unable to connect to VNSD in vipcInit
dts0100629663Crash after double-click on schematic component in Variant View.
dts0100630994"Cannot generate Schematic view. Finish or cancel previous operation" message from VM when reuse block is included in Schematic
dts0100632331Rename "Propagate Hierarchically" command into "Propagate Properties Hierarchically"
dts0100632334Change default properties in Propagate Properties Hierarchically script
dts0100632337Propagate properties Hierarchically icon is not available in the toolbar
dts0100632404Duplicate IDs detected on opening th design. DxDesigner Diagnostics does not fix the problem permamently.
dts0100632710Viewdraw crash when generating variant view
dts0100632857Failed to package ICE design.
dts0100632960Crash on DxD exit when changes in VM Settings have been made.
dts0100634277Packager does not package new components in migrated schematic
dts0100634650Change default property names in prop_reuse_core.vbs script
dts0100634653Rename command "Propagate Hierarchically" into Propagate Properties Hierarchically"
dts0100635522Remove Propagate Through Hierarchy command from Properties window
dts0100637029Dx crashed when I ran Dx diagnostic checker and FA was runnnig
dts0100637288I can't set PropThruHier and StopPropThruHier properties in the netlist project
dts0100539584Its not possible to rename the design name in the DXD Navigator (only 1 design)
dts0100625769Navigator components do not match with page location
dts0100626019Nets are visible in the Navigator window after unchecking 'display nets and buses'.
dts0100632951Navigator shows wrong information after renaming a net
dts0100635134Navigator shows an unnamed net after deleting a block
dts0100635587Adding new sheet gives incorrect behaviours
dts0100635956Navigator still shows connections after disconnecting a port
dts0100605863PCBFWD: Customer can not use Arguments in "Customize Tools Menu"
dts0100625279In this testcase (hierarchical ICE project) pcbfwd crashes.
dts0100630594Please add PKG_GRP property to the netlist.prp file.
dts0100630612Add PKG_LOCK property to netlist.prp
dts0100631001Wide pin swap does not work in DxDesignerExpeditionPCB netlist designs
dts0100633309The pcbfwd fails just after migration - regression
dts0100629388Packager cannot package the new PADS Flow design.
dts0100626765DxDiagnostic process takes too much time
dts0100615088Japanese menu problem: "File -> Print" daialog has some issues of a Japanese translation.
dts0100632470Altering size of print preview window causes navigation buttons to disappear
dts0100623059Can not edit Instance Value in Properties Window
dts0100623081Ref Designator value not visible in the Properties addin
dts0100625986Project was reloaded and Error 1287: iCDB database update error: Invalid parameter was issued to Output dialog after a pipe character | was used in the net name
dts0100626286Prioperties addin does not allow to use comma character needed to alias nets e.g. A|B,C
dts0100627194Properties addin does not show net / instance names added by ICE (with $ character)
dts0100631681[Linux, Solaris] Focus on wrong edit cell in the Properties
dts0100631748Properties addin does not show a name for a bus bit going through hierarchy
dts0100636993Add NETNAME to Global Signal Name mapping in map.cfg file
dts0100620072Place Reuse Block in Schematic Hangs DxDesigner
dts0100625913DxDesigner crashes after change to ICT schematic with Reuse Block
dts0100631979Duplicate IDs detected after place very simple Logical OnlyReuse Block
dts0100633096RF: Seg Vio when attempting to send schematic from AWR to DxD using the replace option.
dts0100606970CRM is leaving a net with MST topology but having from-tos
dts0100616398Change page title from "New Objects" to "Text".
dts0100616401Rename Nets to Nets and Buses
dts0100630588I get File not found when I choose Settings for netlist project
dts0100634268Strange chars in the settings for vhdl/verilog
dts0100495671Strange rounding in millimeters
dts0100549052Can not use Japanese font in Symbol Editor.
dts0100631373Unable to Save Symbol: Error UID Manager: Object not found
dts0100447920Rules for Open Collector and Open Emitter always display error even if are used in good way
dts0100564958VDRC does not create vdrc.log file if there is no "Log Files" folder i project directory.
dts0100575820DRC-201 does not work correctly
dts0100615921"Un-loaded net" does not work in the case of "PIN" type symbol.
dts0100631988Cross probing from a drc-103 opens a wrong sheet
dts0100635214Connectivity warning drc-103 is displayed twice for bus members
pads 9.1 Customer Beta 6 已经出来：
PADS 9.1 Customer Beta 6
December 2009, Install 12587
Please submit defects for products as instructed below.
-----------------------------------------------------------------------------------------
Defects for PADS Layout, Logic, Router and DxDesigner should be submitted to the Beta products on SupportNet,
which are BETA_PADS_Layout, BETA_PADS_Router, BETA_PADS_LOGIC and Beta_PADS_DxDesigner.
***IMPORTANT*** - Known Issues and Future Changes
-------------------------------------------------
1. DxDesigner and related programs from EE2007.8 are now included in this release.
2. Archiver functionality is now available in the Tools menu of Layout, Logic and Router as well as DxDesigner.
3. During installation there is an error with the post install script "accuparts_dx_postinstall.bat".
See the reference notes below for a list of functional updates and current fixes.
Regards,
The PADS Beta Team
Setup, Licensing, Installation, and Distribution
------------------------------------------------
- Windows XP and Windows Vista Japanese are supported.
- Database formats for Layout, Logic and Router designs have changed.
- You are required to have a licenses file with an exact access date of November 1, 2009 or later to run this release.To determine the Exact Access Date (EAD) of your license file go to mentor support net。
PADS9.1 is a completely separate installation from previous PADS releases, The Installation
path for PADS9.1 is now C:MentorGraphics9.1PADS.While PADS9.1 does not overwrite
previous PADS installations, you should back up your existing PADS installation, designs and
libraries prior to installing PADS9.1.
Fixes/enhancements for HyperLynx Thermal
----------------------------------------
none
Fixes/enhancements for HyperLynx Analog
---------------------------------------
dts0100634577Apex Engine doesn't complete simulation for Digital Models
dts0100636111Infohub Help & Manual Scope incorrectly says "Analysis - Simulation and Signal Integrity with HyperLynx Analog
dts0100634078Eldo MC78xx models are incorrect and do not simulate correctly
dts0100636035The SPICE model libraries do not load when useing Eldo with PADS
dts0100608146Exclude Component not shown in Japanese menu
dts0100608582[Simulation Control dialog] :"DC Sweep Parameters" page --> "Add' doesn't behave correctly.
dts0100616119.option tuning will override user value for eps
dts0100631676Incorrect netlist from distribution dialog
dts0100608021Exclusion should work hierarchically
dts0100614981Eldo behaves different than the other netlist formats
dts0100615983The VHDL Netlister should handle the (Read-in output) by creating an intermediate signal
dts0100615994Wrong netlist when symbol pin number is greater than model port number
dts0100618238VHDL netlister does not handle ports properly
dts0100620878Wrong VHDL code with component array
dts0100622857[Netlister] Netlist error in ports connection with buses
dts0100630659[Netlister] VHDL netlist generated for the attached project is incorrect
dts0100632875[Netlister] Output port is not mapped correctly to the bus connected to it
dts0100632876[Netlister] When Port name is same as bus name, the buffer name will be incorrect
dts0100633267When switching simulator between ELDO and HLA, dxnetlister.ini lost [SpiceHeader] information
Fixes/enhancements for HyperLynx
--------------------------------
dts0100629862HyperLynx BoardSIM export from PADS Layout places plane areas within signal net definition
Fixes/Enhancements for PADS 3D Viewing (Note: 3D Viewer 2.0 is included in PADS 9.1)
------------------------------------------------------------------------------------
dts0100605690Layer 20 (footprint courtyard) is used when generating the 3D view.This causes problems with the new 3D viewer
dts0100635846Component heights are incorrect
Fixes/enhancements for PADS Layout
----------------------------------
dts0100592339Netlist from DxD is wrongly loaded into Layout if Unit attribute in DxD is set to Metric.
dts0100621636PADSLayout hangs when you want to substitutes part with Decal that has 'increaded Layer mode'
dts0100601402Time stamp for Part Type on pcb design is not updated when you modify attributes.
dts0100631451Change label in HYP Export dialog box
dts0100544158Poor outline information sent to 3D Viewer - Beta 3
dts0100547218Gerber preview shows short in the design. But there is no errors if we run clearance check.
dts0100593049PADSPCB_Decal Wizard - RMB opens main window popup if cursor is over a data line or title line (Defect for 9.1)
dts0100593100PADSPCB_Decal Wizard - Default layers for outlines in the decal wizard options should be Silkscreen Top, Assembly Top and Layer_20
dts0100593106PADSPCB_Decal Wizard - Selection pop-up on cells is appearing in the grid controls of decal wizard and decal wizard options dialogs.
dts0100593107PADSPCB_Decal Wizard - Decal Wizard: Create crosshair as two "L"'s (instead of two crossing segments).
dts0100593110PADSPCB_Decal Wizard - Decal Wizard dialog: Default button should put some values for component dimensions in the "Land Pattern Calculator" group.
dts0100622131Pads definition on solder mask is incorect for through hole device type generated by IPC decal wizard
dts0100622230Incorect dimention name in the grid
dts0100622475Placement outline is shifted for generated decal
dts0100622697Preview window displays colors incorectly
dts0100623701Notch for assembly outline should have separate control checkbox
dts0100623736Rounded corner radius is incorect for pads on solder and paste layers if mask expansion is used
dts0100623783Generated decal is collapsed for those specific parameters
dts0100623797Tab order works incorectly for wizard dialog
dts0100624535False pad to pad clearance error is indicated
dts0100628883Distance between pads and silkscreen is incorrect for quad decal
dts0100629011Some pads are not rotated for Polar decal
dts0100629304Preview window blinks after pressing default button in BGA tab
dts0100632350Units groups in the decal wizard and wizard options dialogs are NOT in synch with unit setting in the Tools->Options dialog
dts0100633384When a configuration file is missing used gets a misinforming message
dts0100629345Polar tab does not respect the silkscreen line width parameter
dts0100582679When the "Remove unused pads" feature is used, pads within "copper pour and plane area" keepouts are not removed.
dts0100620173Runtime error while doing Forward to PCB.
dts0100634090Runtime error viewdrawlink on update PCB
dts0100472613Not possible to change parttype with PCB-Decals with different number of terminals
dts0100480393Pour Manager does not consider board - Copper Clearance Rules
dts0100570786Bad flood data creates short across 4 nets which Verify Design did not catch
dts0100605615Boldface not used correctly on "PADS Layout GUI Reference> Options Dialog Box, Grids Tab" help page
dts0100633511Change the help menu item to point to a different book
dts0100632059Altium Designer 2006 file will translate in V2005 translator but crashes at 75% in V9.0.2 translator
dts0100593860DXF and IPC export generate Fatal error occurred while exporting design - operation aborted
dts0100473144Length minimize during move will not work when connection is established to partial route or via.
dts0100629626MACRO - When I run the attached macros, the result dialog box doesn't appear. In previous versions a window would popup listing the number of errors found.
dts0100627987When modeless commond "zc" is used, PADSLayout is freezing.
dts0100633930Too crashes when we export ODB++ for preview.pcb
dts0100636557ODB++ Output error (Fatal error: layer -1 not exported！)
dts0100527420Tool allows to create 'Thermals' for SMD Test Points, which leads to series of issues.
dts0100630528Create PDF - Graphical error in copper (Beta 3)
dts0100631593Create PDF - Some Ref Des are rotated (Beta 3)
dts0100631669In PDF User defined Untipads are not added on CAM Plane layer
dts0100631920Create PDF - Remove Bookmarks for components not included in PDF file(Beta 3)
dts0100635884Creat PDF process request hundred times for component that does not exist in library
dts0100496801Reuse Copy loses Flood Priority, resets all to 0
dts0100419975Remove unused pad does not work for nested planes where the outer plane net was used in the inner planes
dts0100636198Crash when removing via from routing via list
dts0100637331Pads disappear when zooming in/out
dts0100635066"Fatal Data Base Error Number 2012" and crash during opening a design in non licensed mode
dts0100600676Picture and information about UFL dialog window should be updated in FSP (or implementation should be changed)
dts0100621629Strange message appears when you perform UFL in Layout.
dts0100634588Update From Library creates Undo Checkpoint even if no changes are made in the PCB Database
dts0100634589UFL dialog: Remove Selected Items button should be ghosted when no design items are selected.
dts0100634608When you import an ASCII file netlist into a new pcb database the decal and part timestamps are not included.
dts0100634609"B.The part type section contains 6 parts that show ?Different? in the? Content column ?but only one of the six has a value in column ?see line?. Should have a line number on all 6of the items that sh..."
dts0100634613The "see line" of Part LITTLEFUSE-V18AUML2220(located at line 89) shows 195 in the "see line" column but it actually starts on line 193.
dts0100634615Timestamp values are not shown in the Part Type Summary.
dts0100634616Line 136 should not truncate names. Wrap the text to the next line or show the entire value.
dts0100634620"C.Line 644 states the Attributes in the library are 16 and the attributes in the pcb are 18. The actual decal has 18 attributes looking at the actual decal in the library file lenny.d"
dts0100634622"F.Looking at line 682 685 686 the counts are equal yet the comparison field shows not equal. Each of these should have additional lines underneath them showing the actual item that does not compare. ..."
dts0100634637"Looking at REPORT-LIB-UPD-ALL.TXT contains the following errors. (Generated from PCB File LIB-UPD.PCB). e.Line 11221, 11336 states they are not equal yet the 4 lines below that are equal."
dts0100634646Even if you update all the parts using the library update to update them there are still errors when comparing the library to the pcb. Please see REPORT-PARTS-UPD.TXT
dts0100637697Parttype timestamp in PADS Layout is not correct if "Send Netlist" is used - (Beta 5) Could be related to dts0100634641.
Fixes/Enhancements for Logic
----------------------------
dts0100623556Component attributes with a value can not be emptied in Edit Part.
dts0100629839Global switch in options to turn on/off place holder attributes in Logic.
dts0100591808Update Logic Sample Files
dts0100428973ECO/Compare reports No Differences Found when one of the files is read only-should indicate it needs write permission
dts01005929010906021756_PADS_LogicCrashReport
dts0100533663Deleting vias in Via Definition > Via Setup does not work
dts0100630556Autotest detected: "PIN Decals" instead of "Pin Decals" in Update from Library dialog box
dts0100623987Fatal run-time error
dts0100579379Automation method ExportNetList wasn't modified when the number of items to select had increased
dts0100619394Regression: If you edit a part from the schematic and add an attribute the attribute is not included after returning to the schematic
dts0100614860Getting error message 'Fatal Runtime Error' when I try to generate File > Report > Unused
dts0100349358Adding Classes with spaces crashes Logic
dts0100574637More than one net is unknowingly selected in the rules after performing a specific set of steps.
dts0100537702There should be a Select list for each Item. Right now, only the Pin Decal has an individually selectable list.
dts0100537705"Update from Library" should be on context menu when selecting a part or parts.
dts0100552427UpdateFromLibrary cannot handle same part types with different attribute values (in report)
dts0100571175UpdateReport detects hierarchical sheets as CAE-Decals - Beta 9
dts0100579630Alternate PCB-Decals still produces false differences in UpdateReport - Beta 11
dts0100593092PADSLogic_Update from Library - ENH:indicate library name in the report (for library decals, parts)
dts0100618873Header in PADSLogic UFL report should be updated.
Fixes/Enhancements for Router
-----------------------------
dts0100628438Saving file in pads router causes fatal error.
dts0100450331Why can't Blazeroute.ini be populated with the new options in their default conditions, so users don't need to type everything in?
dts0100531461Incorrect parameters in Router
dts0100583129Crash dump
dts0100635895Design verification scheme list not work correctly.
dts0100493262Default Windows dialog is displayed for some controls
dts0100634385Library Not Registered errors when PADS is installed to a directory with spaces
Fixes/Enhancements for Install
------------------------------
dts0100498605Need improved handling of the "lost license" scenario in PADS
dts0100569313PADS "Hardware Key Utility" program to make testing keys and installing/removing drivers much easier for customers
dts0100621527While installing the program got error message "C:MentorGraphics9.1PADSSDD_HOMEcommonwin32libMGCLibDataGrid.ocx" failed to load for Registration.
Fixes/Enhancements for IO Designer
----------------------------------
dts0100635950Layout form Allegor is display incorectly.
dts0100635963Missing brd and hyp filter of types in select path to layout.
dts0100637587IOD display only current fpga on device view (Layout import form allegro).
dts0100638335cadence IOD8.2: Got 'Unknown flow！' error message when trying to import schematic design.
dts0100602206IOD not outputting good Actel PDC file
dts0100633957Wrong recognize diff signal form QSF file
dts0100625917After import QSF some differential signal are doubled
dts0100625992It's impossible to import properly diff signals from pin file if it's use '(n)' convenction of naming diff pairs.
dts0100616628'configurator -uninstall' didn't remove IOD entry from menu start
dts0100621897Poor support for IOD installed as single product.
dts0100630357EE 8.2: Installting IOD 8.2 alone would not register the product on Windows.
dts0100616905IOD does not dump tcl command while import signals from spreadsheet is performed.
dts0100636590Iod deleted all project files.
dts0100629434IOD is not responding for over 13 minutes after selecting GND signal.
dts0100633035Cross probing :highlighted wrong signal in IOD while selectingnet in DxD
dts0100625292Pin swaps are not imported
dts0100616652IOD hangs after minimize die size is run in specific case.
dts0100615802Documentation for IOD8.1 should be improve.
dts0100632600Documentation incorrect in regard to Symbol Wizard.
dts0100614543Write to Local PDB file is not remembered
dts0100617368PADS9.0.2 The builtin 'symbi.1' cannot be exported. The path doesnot exist.
dts0100619265PKG_TYPE and SIGNAL attributes are not exported to ICE in pads flow
dts0100619614Differential buses are not connected on the IOD generated schematic.
dts0100630977Remove design doesn't work.
dts0100632139EE IOD8.2: IOD showed a fatal error when running run.tcl.
dts0100636406EE IOD8.2: IOD crashed after export_all_schematics command was issued.
dts0100625329Importing assignment for diff signals from dxd project does not work
dts0100632195Schematic Update is removing and not adding any power, ground and/or config pins defined as signals and/or added to the PCB symbols in the DxD schematic.
dts0100615847NSE seemed to crash on the 'exit' TCL command on Linux only.
dts0100617458De-scoped I/O Designer for PADS Suite
dts0100620002ANALOGVCC is migrated incorrectly
dts0100620440Inconsistent behaviour in creating differential signal name
dts0100624825Spread functionality of Types Compatibility options for HDL signals
dts0100624857"Project could not be saved" because design name has space character.
dts0100626736Environment variable in .prj file not supported
dts0100632352Llicense dialog - empty license options in 'PADS I/O Designer'
dts0100633373SSO value is calculated wrong for differential signals.
dts0100635946Migration of old database should be improved.
dts0100620449Duplicated signals after importing from HDL and QSF
dts0100636022Crash of IOD while importing vhdl entity.
dts0100616013Wrong HDL created/exported
dts0100617953Space character in design name makes problem for IOD.Error: Top level must be set.
dts0100633055Import PCB Design Wizard: Whole signal is unassigned when one pin type is not compatible with signal type
dts0100597469[BSXE] Importing swap in lpc database results in broken connectivity if component database is not synchronized before
dts0100616740Background on Layout view is always black on Vista 64
dts0100621328Unravel on my design with diff signals causes error messages during applying scenario
dts0100630751Library parser failure while importing schematic into layout database.
dts0100633294Partition name is not displayed on Layout Setup window
dts0100633924Signal names disappear on connectivity window after importing pcb layout
dts0100615858IOD8.1: IOD crashed on the TCL file.
dts0100616812IOD8.1: TCL command, exportsymbol, resulted in an error.
dts0100618901Improving TCL script recorder
dts0100623194IOD8.1: TCL command selectsignals A caused IOD to crash.
dts0100631902License dialog is empty on linux after running IOD (refresh problem)
dts0100632077EE IOD8.2: Available license options were not shown for the full version IOD.
dts0100632627Some option related to die database are redundantly displayed in Tools menu for other databases.
dts0100633752EE IOD8.2: IOD crashed on running the TCL file on Linux
dts0100634470EE IOD8.2: IOD crashed when I tried to use TCL commands to select signals after running a Dx VBS script.
dts0100635370EE IOD8.2: IOD crashed with C++ Runtime Library error when adding a new FPGA design.
dts0100638815IOD crashes while openning customer's database on Linux.
dts0100597062Export to AIF from package dbis not required after applying swap on layout db
dts0100607448Import package cell preserving assignments where possible
dts0100628060Error message after reimporting cell into package database with diff signals
dts0100629676Unassign all => cannot unassign signal 'diff_test' - signal diff_test doesn't exist
dts0100605036Types Compatybility does not support an assignment exception
dts0100619916There is no possibility to assign differential signal to pins 8 and 9 in Altera's device.
dts0100624059IOD is not responding while assigning pcb signal with Shift pressed.
dts0100632373Error while importNetlist file (Spreadsheet): .csv, when signal type charakter are small
dts0100632383No assing differential signal (but no DIFF type) afterImport Netlist Spreadsheet file: .csv
dts0100632619Cannot assign output IO signal
dts0100623389'View pins from other devices' doesn't show common pins. Pins list is empty.
dts0100635506IOD is repositioning windows constantly depending on cursor position what looks like IOD is blinking.
dts0100621902Database Settings not prompted when loading FPC.
dts0100631933Creating net-list project ends with error
dts0100633129EE IOD8.2: Got an error on Linux: vmwlm: [11:14:40] error VMWLM0301: License server not found.
dts0100633480EE IOD8.2: IOD failed to create a new project on Solaris.
dts0100626020Rule engine operators have incorrect English
dts0100635228Input pad with INPUT TERMINATION has to be at least 1 LAB away from differential pad.
dts0100635867Rule: Single-ended output and differential signals assignment" work unproperly.
dts0100619597Unplaced tab improperly shows connectivity problems in some case.
dts0100619601Symbol Wizard does not place all signals on PCB symbols in specific case.
dts0100619941Wrong information of selected differential signals.
dts0100620427Corrupted database structure
dts0100619606After splitting bus signals symbols become broken.
dts0100619852It is not possible to exit from mode of adding items (like arc, circle) with ESC key.
dts0100632577IOD writes to transcript some redundant information while symbol edition.
dts0100618530IOD crashes after manipulating signals in the last step of symbol wizard.
dts0100619946Symbol wizard doen't generate symbols with differential signals in specific case. Refresh problem.
dts0100619965'create bank power symbols' is not set up after rerunning symbol wizard.
dts0100626048Sym Wizard assigning incorrect power signals to pins.
dts0100628170Broken PCB symbols after updating.
dts0100629352Symbol Wizard settings 'split only pcb symbols' were not stored in fpc.
dts0100632906Design tool selection dialog is redundant because it is determined before project creation.
dts0100635477IOD crashes while Symbol Wizard performs symbol update
dts0100548702Synchronization wizard in relation to Export cell from die should be corrected.
dts0100596151Synchronization needs to be less sensible. Moving non-IOD symbol shouldn't request import necessity etc.
dts0100599155[Synch. wizard]Export Connectivity table is not available on Synch. Wizard
dts0100606842Everything is matched, however SW indicates, that synchronization is needed.
dts0100614895Gray synchronization indicator sometimes blinks
dts0100617886IOD does not request updating symbols after unraveling (some assigned pins are not placed on PCB symbols)
dts0100617937Synchronization bubbles are yellow while no tracked file export/import is needed.
dts0100619881"Document needs import " during exporting schematic for all components
dts0100624493[Synch. Wizard] Tracking check box does not work properly on Files View for DCDV files
dts0100628627Incorrect export sequence: CES and schematic, but should be opposite. Lost constraints.
dts0100628925[Synch. Wizard] Connectivity Table checkbox is sorted and causes CES disappears
dts0100631718[Synch. Wizard]Import schematic is not required on new layout database
dts0100632062Synchronization wizard contains not added files just after creation fpga database
dts0100633995Lack of 'update graphics' in Synch. Wizard for Schematic Design import.
dts0100635491Import schematic is not requested in synchronization wizard after it is packaged (refdes changed)
dts0100620177Poor results of unraveling for attached testcase.
dts0100629113Unravel of crossover nets is broken.Immediate fix needed.
dts0100631688Unravel on layout database does not work
dts0100491672IOD crashes with PROLOG SYSTEM ERROR when unraveling nets in device view
dts0100636192Broken connectivity in Device View - Synchronization Wizard suggest no action. Database corrupted.
dts0100632012Incorrect warning message during export to UCF file.
dts0100633340Change default bus brackets for Xilinx UCF.
dts0100614926Please add support for ISE 11.2 library.
dts0100616172IOD needs to support the Spartan 6 devices.
dts0100368440IO standard has not been removed from ucf.
dts0100622444Redundant signal is imported from ucf: mcb3_dram_dq.
dts0100622447IOD should not remove from ucf: TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"2.5ns HIGH 50 %;
Fixes/Enhancements for DxDesigner from EE2007.8
-----------------------------------------------
dts0100586982ict viewer has a menu pick for slice and dice, but no documentation for this function.
dts0100566586Icon for deisgn path for additional symbol translation in Translation result dialogis wrong
dts0100567745Cadstar pin types are translated incorectly
dts0100592920CCZ output: Text has wrong orientation in CCZ file for symbols that have been rotated 180 degs or flipped
dts0100633799Verify: drc-201 reports an error when there is none.
dts0100595040Diffpair Restrict Layer Changes does not BA by existing ECO file
dts0100619515It is impossible perform BA using DxDesignerLink
dts0100633269DxArchiver is completely not usable for big designs
dts0100627152The selected component pin object can't be got.
dts0100636979DxDesigner crashes when quit command is invoked and DxDiagnostics is running
dts0100637220DxDesigner crushed when attribute is added by Automation Comp.AddOats / Comp.AddAttribute.
dts0100631832Launching Dx resulted in an error of missing prop_reuse_gui.vbs.
dts0100626155While crossprobing pins in Expedition, DxD crash. Scott was in DxD as well in the page that was being crossprobed to at the time.
dts0100631134Documentation incorrectly refers users to circle object if they want to create an ellipse
dts0100614450Live Verify fails when using the option "Use symbol data from Central Library".This appears to be a regression from EE2007.6.
dts0100614912ListBoxes to create query on dxdb grid display always all values from specific column during query creation.
dts0100615165Japanese menu problem: In the pull-down which selects the slot of DxDB, displays of "Slot" translated into Japanese are not all displayed.
dts0100616337"Part Number: invalid identifier" error during verification with oracle database when "Use symbol data from Central Library" option is set.
dts0100616340"Query is too complex" error during verification with some central libraries and "Use symbol data from Central Library" option set.
dts0100616953Closing and opening DxDataBook may cause disappearing icons on CL view tab.
dts0100616993"Query", "Criteria" and "！" buttons are disabled after loading component.
dts0100617241Export symbol(s) works differently if run from DxDataBook pop-up menu and NSE File menu option
dts0100617992There is a error after selecting tables joined horizontally.
dts0100618179When placing components from DxDatabook it don not change "," comma to a "." dot as it do in 9.0PADS, this result in error when doing netlist.
dts0100629771The query can not be created on the grid after selectinglibrary.
dts0100629777The verification buttons in databook can be enabled with Interconnectivity Table in one case and it can cause errors.
dts0100632306In a Netlist Flow Project we cannot Select multiple Symbols in Symbol Tab of CL view of DxDataBook
dts0100632348A message error is displayed during query creation on the grid for ALL library in some conditions.
dts0100632402"Clear the Current Search" option does not clear a grid displayed forlibrary.
dts0100632407Button 'Enter user / password' is truncated on Japanese WinXP
dts0100632412"Remove Condition" does not work inlibrary.
dts0100632708Verification in DxDatabook crashes viewdraw(regression to 2007.7)
dts0100634366Crash library wizard during creating horizontal table for expedition flow.
dts0100637275Crash during hierarchical verification on specific project.
dts0100372438DxPDF EXP2005.1 generates smal dots instaed of text on Solaris 8 and 9
dts0100541964DxPDF pager order does not work based on the scout SHEET order property.Please reference DR 541962.
dts0100631034DxPDF crashes if "Schematic Sheet Order Property" is used
dts0100633031Please correct the message'Genration ICTs to PDF document (with conversion ICTs to schematics).'
dts0100602277Pin number will not be displayed if Pin Label are either lower or mix case.
dts0100603902"Add Missing ports" on an IO Designer generated schematic for DxDesigner the ports are placed outside the schematics.
dts0100608356Cannot read correct coordinates of scaled symbols in DxDesigner
dts0100611157Part View place with slot fails with lowercase pin names
dts0100615128In the "Find and Replace Text"dialog, the "Select properties only" option is not translated into Japanese.
dts0100615499Japanese menu problem: "Select object > RMB > Pop-up menu" dialog has some issues of a Japanese translation.
dts0100616656Problem with move schematic
dts0100616682Multiple Signal properties are lost when importing ExpeditionPCB netlist design to ExpeditionPCB iCDB integrated flow
dts0100616955Symbol is not updated on schematic when editing it in NSE
dts0100617637DxDesigner must support metric symbol format
dts0100618285Properties addin does not show a name of a net ripped from a bus.
dts0100619905Clear Backups should be inactive for a read only schematic.
dts0100619942iCDB error when placing an updated symbol
dts0100620246Escape does not apply to Rip Net command
dts0100621606Update bus signals removes one of the bus names
dts0100621892unnamed bus segment created after renaming a bus
dts0100622476Push Schematic does not reflect sheet order
dts0100622848DxD Diagnostics reports invalid net errors after moving a component
dts0100623038It si not possible to add ICE Reuse Block to schematic
dts0100623061Enhance Add Properties Dialog
dts0100623427[Linux, Solaris]Show Strokes option doesn't work properly
dts0100624036'DxDesigner application has encountered a problem and needs to close' is not closed when restart is chosen.
dts0100624188add special component; [esc] does not work
dts0100624193Change the message issued when a user types an illegal regular expression
dts0100624578Endless bus created when connecting to an off grid component
dts0100624782Symbol of the array component contains block name.
dts0100624866Invalid global net created
dts0100624886DxDesigner diagnostics fails to correct errors in an imported design.
dts0100626698While crossprobing in CES, DxD crash.
dts0100628557viewdraw crashes when there is no write access to WDIR
dts0100628735Error 1287 when trying to delete bus segment. Diagnostics results in schematic that cannot be opened in schematic or block view.
dts0100628911Modify delete sheet message when this option is chosen from the Navigator
dts0100629037'Error 1287: iCDB database update error: Invalid parameter' when updating bus signals
dts0100629072Select all symbols on a sheet and deleting the Ref Designator property values, wrongly adds Ref Designator property to symbols that didn't have it previously.
dts0100629389DX2PADS changed interface - update in DxDesigner is needed.
dts0100629746DxDesigner Diagnostics large memory allocation on this testcase
dts0100629772Buses and bus rippers disassociation when moving a circuitry around
dts0100629789Connectivity errors in a design created from the scratch.
dts0100630095Shorted nets after renaming a bus
dts0100630174[Linux] DxDesigner crash when I press Undo
dts0100630197Diagnostics error after changing bus ripper connection using 'Net is being connected to bus' dialog.
dts0100630199I get Commit iCDB database transaction rejected. Reloading project when I choose rollback
dts0100630678Wrong connection with GND and diagnostic errors after schematic modification
dts0100630683I get GPF when I press Undo
dts0100630691Incorrect global net name after merging two nets
dts0100630706Wrong connection has been created after updating bus signals in the project
dts0100630958"Push to schematic" does not work after using "extract schematic" during placing new block (regression to 2007.8.12157)
dts0100630973Problem with DxDataBook window when I change expedition project in to netlist
dts0100631052viewdraw crashes when in a text being added to the schematic Unix like end of line characters are used (0A)
dts0100631270I got error: "Can't open symbol definition for schematic block！"
dts0100631630I get Error: Schematic block 'Schematic1.1' has elements with duplicate IDs needed for Backup/Rollback and copying
dts0100631663Renaming a hierarchical connector connected to a global net might create an invalid global net.
dts0100631721Navigator shows incorrect connections for hierarchical bus bundles
dts0100631730Placing a composite with Add Nets and Add Net Names adds a net for a pin using bus bundle name.
dts0100631935iCDB transaction rejected - project was reloaded when three users were pasting sheets at the same time
dts0100631973I get GPF when I choose Undo option
dts0100632623New Project dialog -> Advanced does not set paths to the cns and cfg files.
dts0100632639Rollback option does not work properly
dts0100632669Rollback not save correct design state after backup fixed by DxDiagnostic schematic
dts0100632681"Commit iCDB database transaction rejected" and eventually DxDesigner hangs when running packager and pasting sheet at the same time
dts0100632963[Concurrent mode] DxDesigner crashed when first user was deleting some sheets and other user attempted to delete one sheet right after he opened the design
dts0100633301Cannot package design just after migration - regression
dts0100633970DxD Diagnostics reports connectivity errors after undoing nets renaming
dts0100634006viewdraw crashes when exporting connectivity from ICT
dts0100634010When viewdraw is restarted automatically via the crash handler ('Restart the application and open the recent project') it consumes 100% CPU and is unusable
dts0100634021I get GPF when I choose Flip for ripper symbol
dts0100634256crash dialog has some issues on Windows XP Japanese
dts0100634305Issues with a DxD Diagnostics 'Test: Top Level Name Consistency'
dts0100634332Incorrect connections detected by DxD Diagnostics after copy-paste a schematic sheet
dts0100634819I get DxDesigner is Offline mode when I connect symbol with nets
dts0100635233DxD Diagnostics fails to fix 'Top Level Name Consistency' error in one pass
dts0100635581DxDesigner crashed after nets deletion
dts0100635605I get GPF when I choose Mirror option
dts0100635619I get GPF when I choose Flip option
dts0100635865I get Error 1287: iCDB database update error: when I press Undo
dts0100635936Problem with connection when I change size for bus
dts0100635972viewdraw crashes when flipping a bus ripper
dts0100636130Japanese menu problem: RMB popup menu of component and Block.
dts0100636316Propagate Properties Hierarchically locks all the project sheets (locks remains after it finishes)
dts0100636336During copy paste scenario, creating new sheet creates it in the wrong schematic.
dts0100636675I get Error 1287: iCDB database update error when I press Undo
dts0100569325Copy sheet does not copy block hierarchy when copying constraints is turned off
dts0100626105DxDesigner does not undo and error message Error 1296: Duplicate IDs detected
dts0100635209New DxDesigner Crash Catcher Dialog Details button should be removed
dts0100634336DxD crashes after replace when ODBC(Text, CSV) alias doesn't exists.
dts0100605359HDL: the Unmap option sends vdel command
dts0100608880HDL: Add zoom in/zoom out options to zoom inside the Waveform window
dts0100615226Migrration on design with $ARRAY attribute stops without clear message what is wrong
dts0100615987HDL: waveform stops displaying values after 100 ns
dts0100617492Using Builtin ports IN and OUT in schematic gets reversed in the generated VHDL code
dts0100617927HDL: the HDL Target Library for HDL Design can be set as the Modelsim system library
dts0100620510HDL: cannot simulate configuration for attached design
dts0100621591HDL Simulation settings. ModelSim executable file should explicitely mention vsim.exe
dts0100621605HDL: the path to the external text editor is truncated when it contains space
dts0100621903Cumbersome handling of leaf components
dts0100622290External Dx-ModelSim Flow: Unable to backannotate sim values into schematic
dts0100625569HDL: problem with the path to hdl file attached to component
dts0100625915Crash when setting the Modelsim executable folder
dts0100627635Setting notepad++ as external text editor and then changing it causes runtime error
dts0100627645Changing the default external text editor has no affect until DxDesigner is restarted
dts0100630111Library is not shown in the HDL Libraries window when it has name with dash "-"
dts0100630591HDL: signal names with signs , -, + and space are wrongly exported to vhdl/verilog
dts0100631341Inclomplete simulation macro for Modelsim
dts0100633001HDL files are duplicated in the Project Navigator - regression
dts0100634318Cannot set simulation top level when using ModelSim 6.3a SE as internal simulator
dts0100635137The HDL Search Paths entries are doubled each time I export vhd/verilog netlist
dts0100635583Viewdraw crashes when editing hdl file, but the path to the external text editor is not filled
dts0100629187DxDesigner Diagnostics does not fix the attached project.
dts0100632498MGC_REMAP_RSCM does not work with server:port format
dts0100620443I get Error: (521) [Block fghf] Cannot change interface of symbol placed on schematic when I delete for block or net
dts0100625205Reference designators for elements from fub in ICT, project explorer and Properties window are displayed incorrectly (U? R?)
dts0100629327Constraints are lost after rollback in ICE based design
dts0100629380File->Rollback removes a design from Navigator tree
dts0100631286Symbol Update -> Clear All Highlights does not seem to work in ICE documents
dts0100631297RMB menu 'Symbol Update' does not work in ICE based netlist projects
dts0100631302It is possible edit Read Only RB in ICE
dts0100592947DA2DX did not rename the Supply Rename value
dts0100593885DXD can not package if a hierarical symbol have vector pins nd the internal sheets have single ports for buss pins
dts0100600087few DA hierarchal blocks are translated into Blocks but not into Designs level
dts0100596003DC2DA and DxDesigner need to support LineStyle6-LineStyle16 from Design Capture.
dts0100630918"Unable to open Central LIbrary" error message with the "Create local DxD symbols from DC schematic" option enabled
dts0100631073Translation from DC to DXD causes Duplicate IDs that cannot be repaired using DxDesigner Diagnostics
dts0100615611Orcad Schematic to DxDesigner 2007.5 Translator should have the option to set all colors to "automatic"
dts0100622712The customer has an Orcad Capture schematic, which he converted to DxD. The schematics look fine, but when he generates the netlist and opens PADS Layout he finds a wrong connection (short-circuit).
dts0100624063Pin types migrated incorectly
dts0100625630Unexpected fatal error occured when there is no path to file in Browse frame
dts0100632606Specified file is corrupted or incorrect after import ffs file into DxDesigner using LineSimLink
dts0100633786Incorrect documentation - Importing from HyperLynx with LineSimLink
dts0100619566Export ccz - rotated properties are incorrectly exported
dts0100619652DxD Packager dialog has incorrect text
dts0100622705Solaris - File->Export->Analog netlist does not work
dts0100624832[Linux] Viewdraw crashes after Replace part when data source is ODBC compatible.
dts0100624912Add hierarchical property propagation script to the install
dts0100625050Schematic sheet cannot be opened after updating EE2007.3 project to EE2007.5, EE2007.6 OR EE2007.7
dts0100626477[i]/2007.8EE/docs/data/DxWDIR.zip design not working
dts0100626672pdbslot crashes DxDesigner
dts0100627156IOD cannot create Design. vipc: Error 1347: Unable to connect to VNSD in vipcInit
dts0100629663Crash after double-click on schematic component in Variant View.
dts0100630994"Cannot generate Schematic view. Finish or cancel previous operation" message from VM when reuse block is included in Schematic
dts0100632331Rename "Propagate Hierarchically" command into "Propagate Properties Hierarchically"
dts0100632334Change default properties in Propagate Properties Hierarchically script
dts0100632337Propagate properties Hierarchically icon is not available in the toolbar
dts0100632404Duplicate IDs detected on opening th design. DxDesigner Diagnostics does not fix the problem permamently.
dts0100632710Viewdraw crash when generating variant view
dts0100632857Failed to package ICE design.
dts0100632960Crash on DxD exit when changes in VM Settings have been made.
dts0100634277Packager does not package new components in migrated schematic
dts0100634650Change default property names in prop_reuse_core.vbs script
dts0100634653Rename command "Propagate Hierarchically" into Propagate Properties Hierarchically"
dts0100635522Remove Propagate Through Hierarchy command from Properties window
dts0100637029Dx crashed when I ran Dx diagnostic checker and FA was runnnig
dts0100637288I can't set PropThruHier and StopPropThruHier properties in the netlist project
dts0100539584Its not possible to rename the design name in the DXD Navigator (only 1 design)
dts0100625769Navigator components do not match with page location
dts0100626019Nets are visible in the Navigator window after unchecking 'display nets and buses'.
dts0100632951Navigator shows wrong information after renaming a net
dts0100635134Navigator shows an unnamed net after deleting a block
dts0100635587Adding new sheet gives incorrect behaviours
dts0100635956Navigator still shows connections after disconnecting a port
dts0100605863PCBFWD: Customer can not use Arguments in "Customize Tools Menu"
dts0100625279In this testcase (hierarchical ICE project) pcbfwd crashes.
dts0100630594Please add PKG_GRP property to the netlist.prp file.
dts0100630612Add PKG_LOCK property to netlist.prp
dts0100631001Wide pin swap does not work in DxDesignerExpeditionPCB netlist designs
dts0100633309The pcbfwd fails just after migration - regression
dts0100629388Packager cannot package the new PADS Flow design.
dts0100626765DxDiagnostic process takes too much time
dts0100615088Japanese menu problem: "File -> Print" daialog has some issues of a Japanese translation.
dts0100632470Altering size of print preview window causes navigation buttons to disappear
dts0100623059Can not edit Instance Value in Properties Window
dts0100623081Ref Designator value not visible in the Properties addin
dts0100625986Project was reloaded and Error 1287: iCDB database update error: Invalid parameter was issued to Output dialog after a pipe character | was used in the net name
dts0100626286Prioperties addin does not allow to use comma character needed to alias nets e.g. A|B,C
dts0100627194Properties addin does not show net / instance names added by ICE (with $ character)
dts0100631681[Linux, Solaris] Focus on wrong edit cell in the Properties
dts0100631748Properties addin does not show a name for a bus bit going through hierarchy
dts0100636993Add NETNAME to Global Signal Name mapping in map.cfg file
dts0100620072Place Reuse Block in Schematic Hangs DxDesigner
dts0100625913DxDesigner crashes after change to ICT schematic with Reuse Block
dts0100631979Duplicate IDs detected after place very simple Logical OnlyReuse Block
dts0100633096RF: Seg Vio when attempting to send schematic from AWR to DxD using the replace option.
dts0100606970CRM is leaving a net with MST topology but having from-tos
dts0100616398Change page title from "New Objects" to "Text".
dts0100616401Rename Nets to Nets and Buses
dts0100630588I get File not found when I choose Settings for netlist project
dts0100634268Strange chars in the settings for vhdl/verilog
dts0100495671Strange rounding in millimeters
dts0100549052Can not use Japanese font in Symbol Editor.
dts0100631373Unable to Save Symbol: Error UID Manager: Object not found
dts0100447920Rules for Open Collector and Open Emitter always display error even if are used in good way
dts0100564958VDRC does not create vdrc.log file if there is no "Log Files" folder i project directory.
dts0100575820DRC-201 does not work correctly
dts0100615921"Un-loaded net" does not work in the case of "PIN" type symbol.
dts0100631988Cross probing from a drc-103 opens a wrong sheet
dts0100635214Connectivity warning drc-103 is displayed twice for bus members
Mentor不這樣怎麼搞錢.
2010/1/15 正式发布了9.1
没有太大的更新哦！在功能上！
多谢！
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