如何阅读PADS中的一些报表

请教怎么读以下两份报表。第一份如下：
Powerpcb ECO Generator (Version 6.0) 2009-3-10 13:55:06
Copyright (c) 1995-2001 Innoveda, Inc. - All rights reserved
ASCII reading (part types and decals) - 0 msec
ASCII reading (part types and decals) - 10 msec
Reading the Schematic
WARNING: Signal CHGND has 1 pins
There are 53 parts in the design
There are 29 signals in the design
There are 112 pins in the design
ASCII reading (parts, nets, attributes) - 19 msec
Reading the PCB
There are 53 parts in the design
There are 29 signals in the design
There are 113 pins in the design
ASCII reading (parts, nets, attributes) - 21 msec
Final cost=660
Partitioning - 1 msec
Final Matching - 3 msec
Deleted pins: 13,Added pins: 14
我只明白其中一部分。请问msec是什么？
第二份如下：
*pads-ECO*
*REMARK*old file: C:padspwrLogicFilespadsnet.asc
*REMARK*new file: C:padspwrLogicFilesppcbnet.asc
*REMARK*created by ECOGEN (Version 6.0) on 2009-3-10 13:55:06
PART DIFFERENCES
----------------
Schematic PCB
Ref-des Part-typeecal Ref-des Part-typeecal
R5 07010711R1W R5 R2W-200:R2W-200
Q2 J5027-R:J5027-R Q2 TO-220-3XA:TO-220-3XA
D2 STPR1620CT:TO-220AB-STPR1620CT
P1 TPAD-5-3.5MM P1 TPAD-5-3.5MMAA
Q3 TO-220AB:TO-220AB
NET DIFFERENCES
----------------
Schematic PCB
$$$1
$$$10333
$$$17122
$$$2
SWAPPED GATE DIFFERENCES
------------------------
Schematic PCB
SWAPPED PIN DIFFERENCES
------------------------
Schematic PCB
UNMATCHED NET PINS IN Schematic
-------------------------------
$$$10246 R5.1 Q2.2
$$$10333 C21.2 R5.2
$$$17122 R2.1 J3.1
$$$21225 Q2.3
$$$6682 R2.2
$$$8119 D2.1 D2.2 U3.6
+30V D2.3
CHGND J3.3
UNMATCHED NET PINS IN PCB
-------------------------
$$$1 Q3.1 Q3.2 U3.6
$$$10246 R5.2 Q2.3
$$$10333 R5.1 C21.2
$$$17122 J3.1 R2.2
$$$2 P1.1 J3.3
$$$21225 Q2.2
$$$6682 R2.1
+30V Q3.3
ATTRIBUTE DIFFERENCES
---------------------
Attribute Level [ Schematic Parent -> PCB Parent ]
Attribute Name Schematic Value PCB Value
谁能帮我解读一下么？谢谢

怎么会出现笑脸？不是我加的，可能是冒号：的缘故。不好意思

没人帮忙看看哦

msec是毫秒

第二个这个是说你的设计存在的问题，网表和PCB的网络不一致，这个不会看不懂吧？
1，R5，Q2,D2,P1在原理图里和PCB里的器件封装信息不一致
2，PCB上比原理图多出了4个网络
3，你在PCB里的网络连接关系和原理图发生了变化。

回复6楼：不是完全懂。是直接在PCB DECAL里面改封装的缘故，应该问题不大哦。

这个你还是注意一下，有时候可能一时的大意，你的设计就出问题了，呵呵

恩，还好，还要评审。毕竟一个人的能力是有限的