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proteL99SE中PCB进行DRC时出现如下错误信息怎么回事?

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ProtelDesignSystemDesignRuleCheck
PCBFile:DocumentsPCB1.PCB
Date:7-Mar-2009
Time:21:02:31
ProcessingRule:WidthConstraint(Min=10mil)(Max=10mil)(Prefered=10mil)(Disabled)(Ontheboard)
RuleViolations:0
ProcessingRule:WidthConstraint(Min=10mil)(Max=20mil)(Prefered=20mil)(Ontheboard)
RuleViolations:0
ProcessingRule:RoomSheet1(Region=(-260mil,203.238mil,-259.989mil,2328.188mil)(hasfootprint0805AndIspartofComponentclassAllComponentsAndIsincomponentC1)
ViolationbetweenComponentC1(49560mil,49700mil)TopLayerand
RoomSheet1(Region=(-260mil,203.238mil,-259.989mil,2328.188mil)(hasfootprint0805AndIspartofComponentclassAllComponentsAndIsincomponentC1)
RuleViolations:1
ProcessingRule:HoleSizeConstraint(Min=1mil)(Max=100mil)(Ontheboard)
RuleViolations:0
ProcessingRule:ClearanceConstraint(Gap=10mil)(Ontheboard),(Ontheboard)
RuleViolations:0
ProcessingRule:Broken-NetConstraint((Ontheboard))
RuleViolations:0
ProcessingRule:Short-CircuitConstraint(Allowed=NotAllowed)(Ontheboard),(Ontheboard)
RuleViolations:0
ViolationsDetected:1

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