100个最小化SI问题的通用设计规则：

摘自PrenticeHall-SignalIntegritySimplified：
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AppendixA.100GeneralDesignGuidelinestoMinimizeSignal-IntegrityProblems
Neverfollowaruleblindly.Alwaysunderstanditspurposeandputinthenumberstoevaluateitscost/benefitforyourspecificdesign.
0.Alwaysusethelongestrisetimeyoucan.
A.1MinimizeSignal-QualityProblemsonOneNet
Strategy:Keeptheinstantaneousimpedancethesignalseesconstantthroughoutitsentirepath.
Tactics:
1.Usecontrolled-impedancetraces.
2.Ideally,allsignalsshouldusethelow-voltageplanesastheirreferenceplanes.
3.Ifdifferentvoltageplanesareusedassignalreferences,thereshouldbetightcouplingbetweenthem.Dosobyusingthethinnestdielectricyoucanaffordandmultiple,low-inductancedecouplingcapacitorsbetweenthedifferentvoltageplanes.
4.Usea2Dfieldsolvertocalculatethestack-updesignrulesforthetargetcharacteristicimpedance.Includetheeffectsofsolder-maskandtracethickness.
5.Useseriesterminationforpoint-to-pointtopologies,whethersingleorbidirectional.
6.Terminatebothendsofthebussinamultidropbus.
7.Keepthetimedelayofstubslessthan20%oftherisetimeofthefastestsignals.
8.Placetheterminatingresistorsasclosetothepackagepadsaspossible.
9.Don'tworryaboutcornersunless10fFofcapacitanceisimportant.
10.Followthereturnpathofeachsignalandkeepthewidthofthereturnpathundereachsignalpathatleastaswide,andpreferablyatleast3timesaswide,asthesignaltrace.
11.Routesignaltracesaroundratherthanacrossreturn-pathdiscontinuities.
12.Avoidusingengineeringchangewiresinanysignalpath.
13.Keepallnonuniformregionsasshortaspossible.
14.Donotuseaxial-leadterminatingresistorsforsystemrisetimeslessthan1nsec.UseSMTresistorsandmountthemforminimumloopinductance.
15.Whenrisetimesarelessthan150psec,doeverythingpossibletominimizetheloopinductanceoftheterminatingSMTresistorsorconsiderusingintegratedorembeddedresistors.
16.Viasgenerallylookcapacitive.Minimizingthecapturepadsandincreasingtheantipadclearancediameterwillhelpmakethevialooktransparent.
17.Consideraddingalittlecapacitancetothepadsofalow-costconnectortocompensateforitstypicallyhigherinductance.
18.Routealldifferentialpairswithaconstantdifferentialimpedance.
19.Avoidallasymmetriesinadifferentialpair.Whateveryoudotoonetrace,dothesametotheother.
20.Ifthespacingbetweenthetracesinadifferentialpairhastochange,adjustthelinewidthtokeepaconstantdifferentialimpedance.
21.Ifadelaylineistobeaddedtoonelegofadifferentialpair,additnearthebeginningofthetraceandkeepthetracesuncoupledinthisregion.
22.Itisokaytochangethecouplinginadifferentialpairaslongasthedifferentialimpedanceismaintained.
23.Ingeneral,routedifferential-pairtraceswithastightacouplingaspractical.
24.Decideonedge-versusbroadside-coupleddifferentialpairs,basedonroutingdensity,totalboard-thicknessconstraints,andabilityofthefabvendortomaintaintightlaminatethicknesscontrol.Performancewise,theycanbeequivalent.
25.Foranyboard-leveldifferentialpairs,therewillbesignificantreturncurrentintheplanes,soavoidalldiscontinuitiesinthereturnpath.Ifthereisadiscontinuity,doexactlythesamethingtoeachlineinthepair.
26.Worryaboutterminatingthecommonsignalsonlyifthecommon-moderejectionratioofthereceiverispoor.Terminatingthecommonsignalswillnoteliminatethecommonsignal,justminimizeitsringing.
27.Iflossesareimportant,useaswideasignaltraceaspossible,andneveruseatraceoflessthan5mils.
28.Iflossesareimportant,keeptracesasshortaspossible.
29.Iflossesareimportant,doeverythingpossibletominimizeallcapacitivediscontinuities.
30.Iflossesareimportant,engineerthesignal-viastohavea50-Ohmimpedance,whichusuallymeansdoeverythingpossibletodecreasethebarrelsize,decreasethecapture-padsize,andincreasetheantipad-clearanceholes.
31.Iflossesareimportant,useaslowadissipation-factorlaminateasyoucanafford.
32.Considerusingpre-emphasisandequalizationiflossesareimportant.
A.2MinimizeCrossTalk
Strategy:Minimizemutualcapacitanceandmutualinductancebetweensignalandreturnpaths.
Tactics:
33.Formicrostriporstriplinetransmissionlines,keepthespacingbetweenadjacentsignalpathsatleasttwicethelinewidth.
34.Minimizeanydiscontinuitiesinthereturnpaththesignalsmightcrossover.
35.Ifyouhavetocrossagapinthereturnpath,onlyusedifferentialpairs.Nevercrossagapwithsingle-endedsignalsroutedclosetogether.
36.Forsurfacetraces,keepthecoupledlengthsasshortaspossibleanduseasmuchsoldermaskaspracticaltominimizefar-endcrosstalk.
37.Iffar-endcrosstalkisaproblem,addalaminatelayertothetopofthesurfacetracestomakethemembeddedmicrostrip.
38.Forlong,coupledlengthswherefar-endcrosstalkmaybeaproblem,routethetracesinstripline.
39.Ifyoucan'tkeepthecouplinglengthlessthanthesaturationlength,changingthecouplinglengthwillhavenoimpactonthenear-endcrosstalk,sodon'tworryaboutdecreasingcouplinglength.
40.Usethelowestdielectricconstantlaminateyoucanaffordsothedielectricspacingtothereturnplanescanbekepttoaminimumforthesametargetcharacteristicimpedance.
41.Inatightlycoupledmicrostripbus,thedeterministicjittercanbereducedbykeepingthespacingatleastaswideastwicethelinewidthorbyroutingtiming-sensitivelinesinstripline.
42.Forisolationsinexcessof–60dB,usestriplinewithguardtraces.
43.Alwaysusea2Dfieldsolvertoevaluatewhetheryouneedtouseaguardtrace.
44.Ifyoudouseaguardtrace,makeitaswideaswillfitanduseviastoshorttheendstothereturnpath.Addadditionalshortingviasalongthelengthifitisfreeandeasytodoso.Theyarenotascriticalasthetwoontheends.
45.Minimizegroundbouncebymakingthereturnpathsinanypackagesorconnectorsasshortandaswideaspossible.
46.Usechip-scalepackagesratherthanlargerpackages.
47.Minimizegroundbounceinthepowerreturnpathbybringingthepowerplaneasclosetothereturnplaneaspossible.
48.Minimizegroundbounceinthesignalreturnpathsbybringingthesignalpathasclosetothereturnpathasacceptable,consistentwithmatchingtheimpedanceofthesystem.
49.Avoidusingsharedreturnpathsinconnectorsandpackages.
50.Whenassigningleadsinapackageorconnector,reservetheshortestleadsforthegroundpathsandspacethepowerandgroundleadsuniformlyamongthesignalpaths,orclosesttothosesignalpathsthatwillcarryalotofswitchingcurrent.
51.Allno-connectleadsorpinsshouldbeassignedasground-returnconnections.
52.Avoidusingresistorsingleinlinepackages(SIPs)unlessthereareseparatereturnpathsforeachresistor.
53.Checkthefilmtoverifythatantipadsinviafieldsdonotoverlapandthereisawell-definedwebbetweenclearanceholesinthepowerandgroundplanes.
54.Ifasignalchangesreferenceplanes,thereferenceplanesshouldbeascloselyspacedasyoucanafford.Ifyouuseadecouplingcapacitortominimizetheimpedanceofthereturnpath,itscapacitancevalueisimmaterial.Selectitanddesignitinforlowestloopinductance.
55.Ifmanysignallinesswitchreferenceplanes,spacethesignalpathviasasfarapartaspossible,ratherthanclusteringthemallinthesamelocation.
56.Ifasignalswitchesreferencelayers,andtheplanesarethesamevoltagelevel,placeaviabetweenthereturnplanesasclosetothesignalviaaspossible.
A.3MinimizeRailCollapse
Strategy:Minimizetheimpedanceofthepower-distributionnetwork.
Tactics:
57.Minimizetheloopinductancebetweenthepowerandgroundpaths.
58.Allocatepowerandgroundplanesonadjacentlayerswithasthinadielectricasyoucanafford.
59.Getthelowestimpedancebetweentheplanesbyusingashighadielectricconstantbetweentheplanesasyoucanafford.
60.Useasmanypower-andground-planepairsinparallelasyoucanafford.
61.Routethesamecurrentsfarapartandoppositecurrentsclosetogether.
62.Placeeachpowerviaascloseaspracticaltoagroundvia.Ifyoucan'tgetthematleastwithinapitchequaltotheirlength,therewillbenocouplingandnovalueinproximity.
63.Routethepowerandgroundplanesascloseaspossibletothesurfacewherethedecouplingcapacitorsaremounted.
64.Usemultipleviastothesamepowerorgroundpad,butkeeptheviasasfarapartaspossible.
65.Useviasaslargeindiameteraspracticalwhenroutingtopowerorgroundplanes.
66.Usedouble-bondingonpowerandgroundpadstominimizetheloopinductanceofthewirebonds.
67.Useasmanypowerandgroundconnectionsfromthechipasyoucanafford.
68.Useasmanypowerandgroundconnectionsfromthepackageasyoucanafford.
69.Usechip-interconnectmethodsthatareasshortaspossible,suchasflip-chipratherthanwire-bond.
70.Usepackageleadsasshortaspossible,suchaschip-scalepackagesratherthanQFPpackages.
71.Keepallsurfacetracesthatrunbetweenthepadsofthedecouplingcapacitorsandtheirviasasshortandwideaspossible.
72.Useatotalamountofbulk-decouplingcapacitancetotakeoverfromtheregulatoratlowfrequency.
73.Useatotalnumberofdecouplingcapacitorstoreducetheequivalentinductanceathighfrequency.
74.Useassmallabodysizeforadecouplingcapacitorasyoucanaffordandminimizethelengthofallconnectionsfromthecapacitorpadstothepowerandgroundplanes.
75.Placeasmuchdecouplingcapacitanceasyoucanaffordonthechipitself.
76.Placeasmanylow-inductancedecouplingcapacitorsasyoucanaffordonthepackage.
77.UsedifferentialpairsforI/Os.
A.4MinimizeEMI
Strategy:Reducethevoltagethatdrivescommoncurrents,increasetheimpedanceofthecommoncurrentpaths,andshieldandfilterasaquickfix.
Tactics:
78.Reducegroundbounce.
79.Keepalltracesatleastfivelinewidthsfromtheedgeoftheboard.
80.Routetracesinstriplinewhenpossible.
81.Placethehighest-speed/highest-currentcomponentsasfarfromtheI/Oconnectionsaspossible.
82.Placethedecouplingcapacitorsinproximitytothechipstominimizethespreadofhigh-frequency-currentcomponentsintheplanes.
83.Keeppowerandgroundplanesonadjacentlayersandasclosetogetheraspossible.
84.Useasmanypower-andground-planepairsasyoucanafford.
85.Whenusingmultiplepower-andground-planepairs,recessthepowerplanesandthenstitchshortingviasbetweenthegroundplanesalongtheedges.
86.Usegroundplanesassurfacelayers,wherepossible.
87.Knowtheresonantfrequencyofallpackagesandchangethepackagegeometryifthereisanoverlapwithaclockharmonic.
88.Avoidsignalsswitchingdifferentvoltagereferenceplanesinapackage.Thiswilldrivepackageresonances.
89.Addferritefiltersheetstothetopofpackagesiftheymighthavearesonance.
90.Minimizeanyasymmetriesbetweenthelinesineachdifferentialpair
91.Useacommon-signal-chokefilteronalldifferentialpairconnections
92.Useacommon-signal-chokefilteraroundtheoutsideofallperipheralcables.
93.FilterallexternalI/Olinestousethelongestsignalrisetimethatistolerableforthetimingbudget.
94.Usespread-spectrumclockgeneratortospreadthefirstharmonicoverawiderfrequencyrangeanddecreasetheradiatedenergywithinthebandwidthoftheFCCtest.
95.Whenconnectingshieldedcables,trytokeeptheshieldasanextensionoftheenclosure.
96.Minimizetheinductanceoftheshieldedcableconnectionstotheenclosure.Useacoaxialconnectionrightfromtheendofthecableandtotheenclosure.
97.Equipmentbaysshouldnotpenetratetheintegrityoftheenclosure.
98.Onlyinterconnectsneedtobreaktheenclosureintegrity.
99.Keepaperturediameterssmall,significantlysmallerthanawavelengthofthelowestfrequencyradiationthatmightleak.Moreandsmallerholesarebetterthanfewerandlargerholes.
100.Themostexpensiveruleistheonethatdelaystheproductshipdate.