手机PCB Layout checklist

Item description 

Strategy

Place major components for natural signal flow and special VCTCXO factors

Define general signal flow

Define approximate shielded areas

Begin considering PCB stack-up, via-types, and grounding philosophy

PCB details

Stack-up: metal and dielectric layers, thicknesses, assign functions

Design microstrip and stripline transmission lines; calculate losses

Establish library of via-types; commit to using many

Establish grounding philosophy

Verify component library, including major component land and stencil patterns

Routing, stage 1

Roughly place all components; maintain desired signal flow

Route highest priority traces; iterate placements as needed for clean flow

All RF connections from antenna(s) to RFICs

All RF and LO connections between RFICs, modules, etc.

VCO tuning lines

VCTCXO signals, including buffered TCXO signal to MSM device

Baseband signals (Rx and Tx)

PDM signals

SBI signals

Follow RF guidelines for RF, LO, and other sensitive traces

Controlled-Z techniques (or similar for non-RF/LO); continuous ground

Verify RF/LO trace widths per fabrication drawing

Short, direct traces; avoid crossing RF/LO traces

Stripline for long traces, especially in unshielded areas

Microstrip within shielded areas, especially component interconnections

Avoid multiple transitions between inner and outer layers

Maintain adequate clearance around signal vias in all directions (isolation)

Clear inner layers to minimize parasitic capacitance, improve geometry

Place inductors so that their magnetic fields do not couple

Make paths of differential pairs as symmetrical as possible

No RF/LO traces on outer layer below components

Ground fill for coplanar isolation; stitch to inner ground; adequate spacing

Verify shielded areas encompass the intended circuits and traces

Provide cutout in shield walls for microstrip entrance or exit

Connect ground vias directly to RFIC and component pads

Unbroken ground plane in exposed outer layers, especially near antennas

Isolate antenna currents from noise currents

Make internal ground planes as solid as possible

Surface ground and many vias to internal ground for RFIC ground slugs

See applicable chipset design guidelines document for RFIC matching layouts

Routing, stage 2

Verify that the other board-level considerations are addressed sufficiently

Radiated desensitization

GPS functions

Thermal considerations

Routing, stage 3

Route DC power

Wide traces and sub-planes; proportional to current

Several vias to transition between layers; proportional to current

Avoid loops; use spine structure, branching left and right as needed

Keep high current PA traces & returns away from Rx and VCO functions

Avoid sharing high current traces by PMIC and PA functions

No power traces directly below RFIC pads w/o layer of ground between

Routing, stage 4

Route other (typical) digital traces last

Enable trace crossings by routing on two layers: horizontal and vertical

Wide ground area between RF section and digital section on single layer

Long, indirect traces are okay; work around higher priority traces

Route digital traces to RF areas using digital layer; use ground to isolate