PCB EMC设计首要考虑的10个因素（1）

EMC设计首要考虑的10个因素

随着高速电路需求的日益增加，PCB设计变得越来越富有挑战性。除了PCB的实际逻辑设计，工程师还必须考虑其他几个影响电路的方面，如功耗、PCB大小、环境噪声、以及电磁兼容（EMC）。本文将介绍硬件工程师如何在PCB设计阶段解决电磁兼容问题，使系统不受电磁干扰影响。

1. Ground Planes – A low inductance ground system is the most vital element when designing a PCB for minimizing EMC. Maximizing the ground area on a PCB reduces the inductance of ground in the system， which in turn reduces electromagnetic emissions and crosstalk.

复制代码铺地层 —— 在进行PCB板设计时低感应系数的接地系统对于最小化EMC来说是最重要的元素。最大化PCB铺地面积可以减少系统中铺地自感应，从而减少电磁辐射和干扰。

Signals can be connected to ground using different methods. A poor PCB design is one where components are connected randomly to ground points. Such a design generates high ground inductance and leads to unavoidable EMC issues.

复制代码信号可以用不同的方法连接到地。一个比较差的PCB设计就是器件随便地连接到接地点。这样的设计会产生高的自感应，从而导致不可避免的EMC问题。

A recommended design approach is to have a full ground plane as it provides the lowest impedance as the current returns back to its source. However， a ground plane requires a dedicated PCB layer which may not be feasible for two-layer PCBs.

In such case， designers are recommended to use ground grids as shown in Figure 1a. The inductance of ground in this case will depend on the spacing between the grids.

复制代码推荐的设计方法是，用一整层铺地，这是因为电流回到源端时阻抗很低。然而，专门有一层来铺地对于两层PCB来说是不切合实际的。在这种情况下，建议设计者们使用如图1所示的铺地网格。在这种情况下地的自感应取决于网格之间的距离。

The way a signal returns to system ground is also very important because when a signal takes a longer path， it creates a ground loop which forms an antenna and radiates energy. Thus， every trace carrying current back to the source should follow the shortest path and must go directly to the ground plane. Connecting all the individual grounds and then connecting them to the ground plane is not advisable because it not only increases the size of current loop but also increases the probability of ground bouncing.

Figure 1b shows the recommended method of connecting components to the ground plane.

复制代码信号连接到系统地的方式也很重要，因为当信号路径过长，它就构成了一个地环路，会形成天线和辐射能量。因此，每一个载流回源线迹都应遵循最短路径，必须直接连接地平面。连接单个的地，然后将它们连接到铺地平面是不可取的，因为它不仅增加了电流环路的尺寸，而且还提高了ground bouncing的概率。图1 b显示了器件连接到地平面的推荐方法。

Using a Faraday’s cage is another good mechanism for reducing the problems caused by EMC. A Faraday cage is formed by stitching the ground on the complete periphery of the PCB and not routing any signal outside this boundary (see Figure 1c). This mechanism restricts the emission/interference from/to the PCB within/outside the boundary defined by the cage.

复制代码使用法拉第笼是另一个可以减少EMC引起问题的不错机制。法拉第笼构成是这样的，在整个PCB边界打一些小孔连接到地，边界外面不布任何信号 (参见图1 c)。这一机制可以制约来自定义的笼里面PCB的辐射/干扰，并阻止笼外面的辐射/干扰影响PCB。

2. Component Segregation – For an EMC-free design， components on the PCB need to be grouped according to their functionality， such as analog， digital， power supply sections， low-speed circuits， high-speed circuits， and so on. The tracks for each group should stay in their designated area. For a signal to flow from one subsystem to another， a filter should be used at subsystem boundaries.

复制代码器件隔离 —— 对于一个没有电磁干扰的设计，PCB上的元器件需要按照功能分组，如模拟、数字、电源部分，低速电路、高速电路等。每组的布线应该保持在指定的区域。对于从一个子系统流到另一个子系统的信号，应该在子系统的边界放一个滤波器。

3. Board Layers – Proper arrangement of the layers is vital from an EMC point of view. If more than two layers are used， then one complete layer should be used as a ground plane. In the case of a four-layer board， the layer below the ground layer should be used as a power plane (Figure 2a shows one such arrangement). Care must be taken that the ground layer should always be between high-frequency signal traces and the power plane. If a two-layer board is used and a complete layer of ground is not possible， then ground grids should be used.

If a separate power plane is not used， then ground traces should run in parallel with power traces to keep the supply clean.

复制代码板层 —— 从EMC角度来看，PCB板层结构尤为重要。如果PCB超过两层，那么应该有一个整层用来铺地。在四层板的情况下，铺地层下面应是电源层(图2a显示了这种结构)。必须注意，在高频信号和电源层之间应该有铺地层。如果为双层板设计，不可能有整个铺地层，那么应该使用铺地网格。如果不是独立的电源层，那么应该使用地线和电源线平行来保持供电干净。

4. Digital Circuits – When dealing with digital circuits， extra attention must be given to clocks and other high-speed signals. Traces connecting such signals should be kept as short as possible and be adjacent to the ground plane to keep radiation and crosstalk under control. With such signals， engineers should avoid using vias or routing traces on the PCB edge or near connectors. These signals must also be kept away from the power plane since they are capable of inducing noise on the power plane as well.

While routing traces for an oscillator， apart from ground no other trace should run in parallel or below the oscillator or its traces.

The crystal should also be kept close to the appropriate chips.

复制代码数字电路 —— 在处理数字电路时，需要特别注意时钟和其他高速信号。连接此类信号的走线应保持尽可能短，并靠近铺地层以保持辐射和干扰在控制之下。对于这种信号，工程师应避免使用过孔或者在PCB边缘和靠近连接器的位置走线。这些信号应该远离电源层，因为它们也会在电源层产生噪声。

当给晶振布线时，除了地，其他任何走线都不能与时钟线平行或布在晶振下面。晶体还应该尽量靠近需要时钟的器件。

It is also worth noting that return current always follows the least reactance path.

Therefore， ground traces carrying return current should be kept close to the trace carrying its associated signal to keep the current loop as short as possible.

Traces carrying differential signals should run close to each other to most effectively use the advantage of magnetic field cancellation.

复制代码值得一提的是，电流返回总是沿着阻抗最低的路径。因此，承载返回电流的地线应和相关的信号布线尽量靠近，以保持电流环路尽可能地短。

差分信号布线应该尽可能靠近对方，最有效地利用磁场抵消的优势。

5. Clock Termination – Traces carrying clock signals from a source to a device must have matching terminations because whenever there is an impedance mismatch， a part of the signal gets reflected. If proper care is not provided to handle this reflected signal， larges amount of energy will be radiated. There are multiple forms of effective termination， including source termination， end termination， AC termination， etc.

复制代码时钟匹配 —— 从源端到器件的时钟线必须完全匹配，因为每当有阻抗失配的情况下，就会有部分信号反射。如果没有适当处理反射信号，就会有很大的能量辐射出去。有很多种有效的匹配方式，包括源端匹配，终端匹配，AC匹配等。