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problem with layout via

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Hi all,

I want to make dual side pcb. I have a problem with via which connects cond and cond2.
I defined everything but its not working. I made a test as you can see in the picture. Its a simple wire made from 2 layers. But when I set the schematic, it acts like open circuit !!!


附图/附件


via.png

To complete this type of EM (layout) simulation you also need to map the via shapes you are showing to a Conductor Via through the FR4 layer of the substrate you are showing. This will be able to create the connection between the Top and Bottom layers you have defined and will complete the circuit you are building.

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