Input and output matching for LNA design in ADS

Hello,

I am in process of designing an LNA in ADS. I went through theory behind LNA design and now I understand the input and output matching circuits. However to do the schematic, let?s say for the input matching circuit for an LNA with inductive degeneration, what value of Lg and Ls I have to use? I guess it depends on the parasitic capacitances of my transistor as well. In that case how can I know how much is the parasitic capacitance?

I understand that I have to tune my Ls and Lg values so as to match the real part of impedance and cancel the imaginary part. But I don?t know where I have to start? How to choose the values?

Kindly advise... Thanks in advance...

If you don't know exactly what values they have, use optimization technique to achieve your requirements.
I don't know what frequency you're working on but they have to be few nH level for 1 GHz and beyond.But You have to optimize those values in order to get a right specs.

Thank you for your response...

Other than optimisation, is there an approach to exactly find what values of Ls and Lg we have to use so that input matching will be done. The source resistance is 50 Ohm, Transistor is HBT and frequency is 24Ghz.

What I want to know is how to choose the values as we have to take into account the parasitic caps of the HBTs in ADS. Apologies if my thought process is incorrect.

You should check the Optimum Reflection Coefficient for Lowest Noise target then you can add Ls and Lg to bring up this impedance matched to 50 Ohm.
So the problem is reduced to design a simple matching circuit.

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