Using ADS to design a 802.11p 5.9 GHz PA

Hello everyone,

I am designing a PA for IEEE 802.11p using either one of these transistors:

-http://cdn.macom.com/datasheets/NDS-042r2%20NPT2018%20Preliminary%20datasheet.pdf
-http://www.cree.com/RF/Products/General-Purpose-Broadband-28-V/Packaged-Discrete-Transistors/CGH40010

I did load-pull for both of them and then instead of using source-pull i just used the conjugate of the input impedance seen by the transistor.

I was trying to design my matching networks, but even though they seem very close to what I want (in smith chart) when putting them in the design with the transistor the results detriorate a lot.

The optimization I'm using looks something like doccument1 attached.

I know that then I have to take into consideration the stability analysis and so on, but right now I would like to try and understand why this is happening.
The substrate using is one from Rogers which is able to go up until 10 GHz.

Thanks a lot,

So, you know well the Optimum Load information but you didn't do any Source Pull simulation at this power level ?
The amplifier will surely fail because high power input impedance can-probably will- be quite different than small signal one.This is very common for power amplifiers.For instance,while small signal impedance is 35-j*15 Ohm, high power impedance can be 5+j*10 ( something like that ) due to strong dependency of the s-parameters to operating voltages and currents.
I suggest you do source and load pull simulations both.Or request these measured data from the manufacturer because they have already measured.

Why do you say it fails? Doesn't having the conjugate impedance mean maximum power delivered?
What you are trying to say is that if I have 20 dBm input I will have a certain source impedance and if I have 10 dBm I will have another one?

Large signal impedances-general case- are always different than small signal ones.
20dBm=0.1W
10dBm=0.01W...

The first power is 10 times higher than second one.If we consider the currents-for instance-
0.1W=44.7mA@50 Ohm
0.01W=14.1mA@50 Ohm..

First current is 3 times higher than previous one..

So you can imagine the differences between high power levels low poer levels in terms of transistor characteristics..

So you are suggesting that I do the source pull for the input power corresponding the output power I need? Or to achieve maximum power delivered?

This is the difficulty..
While maximum available power is obtained by source and load pull techniques are applied simultaneously...
There is an optimum combination ( in term of optimum source and optimum load impedance) point so that this point will give you neither max. power nor maximum efficieny.
So, load and source impedance both involve into this phenomena..
In ADS, there are very nice PA Design Guides, why don't you use which is proper for your requirements ?

There are nice PA guides and I used the Load-pull and Source-pull, but separately of course. After doing the Load-pull I selected a point. Then I do source pull.

The problem is that when I try to make the matching network (Let's say for output impedance) my PAE drops like 30% (from 35% to 10% at 1dB compression point) or something like that. Is that related to the substrate I'm using or the technique I'm using for optimization? The substrate is Rogres 4350B (which should go up to 10 GHz).

申明：网友回复良莠不齐，仅供参考。如需专业帮助，请学习易迪拓培训专家讲授的ADS视频培训课程。