cpw ads layout configuration

Finite grounds are drawn, just like regular metal.

Place pins at signal and the grounds, then group them into one port in the port editor, with both ground pins used as the port "minus". This is done by drag & drop in the port editor, to use these pins for explicit ground, instead of the nearest infinite ground plane.

For the ground pins, you need to care about the port size if the metal width is large compared to the wavelength. In this case, you can draw a line that defines the terminal size of the port, see here: http://muehlhaus.com/support/ads-app...edge-area-pins

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If you look at the ADS example files for CPW, most of them use a "slot layer" approach where the inverse (anti-metal = slot) is drawn, and the Momentum substrate is then defined with slot layer instead of metal layer. This is an efficient approach, but the limitation is that metal is then simulated lossless, with zero thickness. For more realistic metal modelling, you really need to mesh the metal (not slot).

If your dielectric substrate is not very thick and the gap is not too close which is between the signal line and next-side GND,you may use VIAS between your next-side GND and true GND ( cover sheet of the disclosure ), you place your signal ports onto stripline as ussual.

Yes, that's a possibility for some PCB layouts, where we have microstrip with additional ground on the sides.
What I discussed above is for "true" CPW lines (no ground below or above).

thank you!

How would the configuration be if the finite ground plane is split into two parts, one is a ground plane connected to ground and the other one is connected to DC current? How I connect a path to DC?

|               |               |               |               |
|    GROUND     |      DC       |      LINE     |     GROUND    |
|               |               |               |               |

Maybe that is the wrong question, because we are interested what your DC line does at RF frequencies. So you need to treat it like an RF line in simulation, and need to know the terminations for these RF frequencies. In general I would say it's a design flaw to have this layout with "DC" line next to the RF line.

I need to have a DC line
Maybe I simulate this DC as a ground line. I am not sure about that

The problem is quite similar to micro strip lines over a split ground plane.

With a sufficient number of reasonably distributed low inductance bypass capacitors, the DC "line" (or copper pour) might act almost as CPW ground. If you want to know exactly, you'll draw the actual dimensions and include the bypass capacitors in the simulation.

I dont understand what you mean

My simulation is a CPW, but I need to add a DC current path. I would like to know how I can model it in ADS in order to calculate the effect of this DC line in the RF simulation.

You don't wnat to hear this, but the much better layout is to place your DC line away from the RF line ! If it is outside the main RF field, shielded by the side grounds, it will be much less trouble.

In your configuration, with the "DC line" inside the CPW, much RF will couple into the "DC line". You can tell the line that it's a DC line, but that is just a name, and doesn't change the physics of coupled lines. Your "DC line" will carry RF signal and you will have trouble with RF leaking around in your cuircuit, distributed via the "DC line" that really has DC + coupled RF.

But if you still want to simulate with the "DC" line in this place, treat it like an RF line. This is the ONLY way to get useful results, because you WILL have coupling between the lines. ONLY if you KNOW the RF impedances at both ends of the DC line, you can use that, otherwise use ports and then check realistic terminations of the "DC line" in postprocessing.

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