In ADS， How to generate the layout for two parallel connected VIA2 grounds.

Dear Sir,
Please help someone else to resolve this difficulty.

I think there are 2 coincided vias.Select one and move..

Sir,
They may be coincided, what we have to connect to separate the two parallel VIA2 ground. They must be automatically separate,when we generate layout. What bend, MCORN, MTEE, we have to use. We should not manually move to separate two parallel VIA2 grounds.Can you tell me.

If you want the layout to be generated automatically without any manual adjustment then you must make sure that you never connect more than two symbols pins together at one connection. That means transistor pin to MLIN pin, MLIN pin to a single VIA2 pin, etc and never MLIN pin to 2 VIA2 pins. So you need to add something that creates two "output" pins from a single "input" pin. Therefore an MTEE with middle pin connected to the MLIN and the 2 opposite pins each connected to a single VIA2.

If the length of the transmission line is tuned then you will need to adjust (shorten) its length to compensate for the additional "length" in the layout of the MTEE. You will also have to adjust the length of the MLIN further to compensate for the "length" added by the connected VIA2 elements.

RealAEL Sir,
Thank you for your help, I am sorry that I didn't understand, what you said in the previous post , can you it show diagrammatically. How we can connect the two VIA2 parallel and generate layout. After layout generation, we shouldn't manually drag and separate it the two VIA2 in the layout, parallel connection of two VIA2 come automatically in the layout. Can you show it diagrammatic connection, how we can get it sir. If we use SINGLE VIA2 instead of two parallel VIA2,we will loose overall gain of the amplifier like anything.

As soon as you try to place the appropriate components in the schematic is should become obvious.

     Transistor
         |
       MLIN
         |
VIA2 - MTEE - VIA2

RealAEL Sir,
As you have shown in the code, I connected and generated the layout. For MTEE widths W1 and W2 , I am taking the adjacent VIA2 ground widths. Is it correct sir, whatever I have generated layout from the schematic , I have shown below, please make it confirm sir, weather it is correct or not (both schematic and layout).

As I have shown in the generated layout figure. at the arrow mark 1 shown in figure, there is no gap appearing between two VIA2 (Is it O.K or there must be gap between two VIA2 ground) . At the arrow mark 2 shown in figure, there is gap between two VIA2.
Here with I am attaching both schematic and generated layout.

I cannot say whether anything is right or wrong. You, as the designer, are the only one who can make that decision. Is the design configuration as required? Does it yield the correct simulation performance? Is it manufacturable or does any part of the design violate some limit set by the board manufacturer? These are questions that you need to answer yourself to say whether the design is good or bad.

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