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how to generate circuit design in ADS using Matlab

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Hi,

I designed a PA in ADS, and now I want to generate the same design many times with few different values. I am using matlab to set the parameters I want to change.

I have 2 problems:
1) I dont really understand the dsn file. How is it generated?I see it contains the variables I want to change, but to be able to create it, i need to know what do the many numbers before the circuit specs represent and how are they generated.
2) What should I call to run the simulation? For momentum it's MomEngine but what is for Transient and or S-param simulation from schematics?

I hope I could explain myself properly and someone can help me or at least direct me to some place where I can read abt this.

Thanks,
Sneza

It is generated from schematic.
But there is one more file, "*.ael" generated from schematics.
So one schematic need two files, "*.dsn" and "*.ael".

I can't understand what you mean.

I can't understand what you mean.

But I don't recommend you to modify or create "*.dsn" and "*.ael" directly.

ADSsim use netlist as same as other simulator such as conventional SPICE.

Edit netlist and run ADSsim from command line.
Here you can generate or modify netlist by MATLAB.

I think partial netlist modification by using '#include "filename"' is useful and effective for your purpose.
http://edocs.soco.agilent.com/displa...r+Input+Syntax

% hpeesofsim [-r output_rawfile_name] [netlist_inputfile_name]
See the followings.
http://www.designers-guide.org/Forum...1265191125/7#7
https://www.edaboard.com/viewtopic.php?t=370016
http://www.designers-guide.org/Forum...62828862/27#27

Anyway if you use netlist and run ADSsim from command line, you can get large flexibility.

Hi
why you dont varying the parameters directly in ADS? I do a same work means i designed a PA in ADS and for my designing i changed many parameters in circuit but in ADS i think its better and simple.

Hi,
@rezaee: I can not vary my parameters in ADS since I need an automated program that runs in matlab creates the circuit, runs the simulation, and read the citi file back in matlab for processing. Another thing is that I need to create 100+ PAs, and need to vary min 10 parameters in the circuit. If I vary more than 2 I already start running out of virtual memory, and sometimes the machine completely blocks :(

@pancho_hideboo: I thought abt the netlists but it doesnt contain all the info I need for the circuit. the transistor I use is not one from the provided packages, but I have actually designed it. So to be more clear, my PA circuit uses a subcircuit which has a model definition.
I looked at the ael file and that seems rather easy to generate from matlab.

Code:

fname = strcat(work_dir, '\networks\circuit.ael');
f = fopen(fname, 'w');
if (f < 0),
  error(sprintf('Unable to open output file %s.', fname));
end

fprintf(f, strcat(...
'user = %s\n',...
'set_simulator_type(1);\n',...
'create_item("circuit","circuit","X",16,-1,NULL,"Component Parameters",NULL,"%43?global %;%d:%t %# %44?0%:%31?%C%:_net%c%;%;%e %b%r%8?%29?%:%30?%p %:%k%?[%1i]%;=%p %;%;%;%e%e","circuit","%t%b%r%38?%:\n%39?all_parm%A%:%30?%s%:%k%?[%1i]%;=%s%;%;%;%e%e%;","SYM_0Port",3,NULL,0);\n',...
'set_design_type(1);\n',...
'library_group("*", "*", 1, "circuit");\n'),...
strcat(p, '/', work_dir));

fclose(f);

I dont get the many % signs but they dont change from circuit to circuit.

What i actually want to do is to create the circuit from matlab. So create the dsn file, the ael file, cfg file and then the citi file which should be the output of the simulation (I guess there should be some other files in between).

I looked at the netlist but it doesnt seem complete to me.
Like it doesnt have the transmission lines from my subcircuit nor the MESFETM1 model definition and parameters (from which i need to vary some) nor the substrate info.
the circuit netlist is missing the P1_Tone port and maybe sth else as well.

Also it doesnt contain the info for simulation. how do I edit that?

I hope I was more understandable in what I want to do now.
Please help me, any help is much appreciated!

Thanks,
Sneza

No.
Netlist includes all informations required for simulation.
So it includes subcircuit definitions and model definitions.

I don't think so.

Output file is "*.ds" not "citi", although we can output as "citi".

It can't be. If so, simulation can't be run.
Again netlist surely includes all informations required for simulation.

Again see all threads after http://www.designers-guide.org/Forum...62828862/13#13

Show me your netlist.

so i looked at the log file for the netlist and there is an error. I guess when it comes to the error it simply stops including the other parameters?
so this is the log file i get:

Code:

Design Name: circuit
Date:        February 22, 2010 11:42:10


ERROR!  Port S1 and port S2 in the design ATF55143 are shorted together.
WARNING! Instance PORT1 of type P_1Tone does not have a netlisting definition.

Netlisting finished at 11:42:10

and this is the netlist:

Code:

* Design Name: circuit
* Date:        February 22, 2010 11:42:10

.subckt ATF55143 G S1 D S2
.param K=5
.param Z1=30
.param Z2=85

CC1 G S1 C=0.143pF
CC2 D S1 C=0.115pF
JFET1 _net403 _net413 _net409 MESFETM1
LL1 G _net413 0.621nH
LL4 S1 _net409 0.238nH
LL6 _net409 S1 0.205nH
LL7 _net403 D 0.778nH
.ends ATF55143

.subckt circuit
.param Pavg=10

.param Rfeed=5100

CC1 0 _net94 C=10000pF
CC2 0 _net123 C=8.2pF
CC3 0 _net93 C=10000pF
CC4 0 _net88 C=8.2pF
CC5 vlow vin C=5.6pF
CC6 Vout _net121 C=2.2pF
LL1 _net121 _net123 10nH
LL2 _net106 _net121 5.6nH
LL3 vlow _net88 2.7nH
RR1 _net123 _net94 18
RR2 vhigh _net106 15
RR3 _net92 _net123 'Rfeed*1'
RR4 0 _net92 910
RR5 _net93 _net92 10
RR6 _net88 _net93 50
VSRC1 _net94 0 3
RTerm2 Vout 0 50
xX1 vlow 0 vhigh 0 ATF55143
.ends circuit


.end

i dont understand the error though. The ATF55143 circuit I include has 2 sources S1 and S1 which in the main circuit are grounded. And when I use only ADS to simulate the S parameters for ex. it works fine.

I tried exporting the netlist from my subcircuit only, and I get the same error. So it seems the problem is there.
I am attaching an image from the subcircuit here.

I am really sorry to bother you this much, but Im rather new in ADS and I need to figure out this automation process rather soon. Thank you so much for your help.

I think very so.
If you can understand ADSsim correctly and undertsnad netlist for ADSsim, you can get large flexibility for ADSsim running.

Here if you know ADSsim versatilities well, even MATLAB is not required for your purpose.

"trans.JPG" is schematic for subsckt.
Show me top circuit.

I think you use "netlist include" in top circuit.

Code:

* Design Name: circuit
* Date:        February 22, 2010 11:42:10

.subckt ATF55143 G S1 D S2
.param K=5
.param Z1=30
.param Z2=85

CC1 G S1 C=0.143pF
CC2 D S1 C=0.115pF
JFET1 _net403 _net413 _net409 MESFETM1
LL1 G _net413 0.621nH
LL4 S1 _net409 0.238nH
LL6 _net409 S1 0.205nH
LL7 _net403 D 0.778nH
.ends ATF55143

.subckt circuit
.param Pavg=10

.param Rfeed=5100

CC1 0 _net94 C=10000pF
CC2 0 _net123 C=8.2pF
CC3 0 _net93 C=10000pF
CC4 0 _net88 C=8.2pF
CC5 vlow vin C=5.6pF
CC6 Vout _net121 C=2.2pF
LL1 _net121 _net123 10nH
LL2 _net106 _net121 5.6nH
LL3 vlow _net88 2.7nH
RR1 _net123 _net94 18
RR2 vhigh _net106 15
RR3 _net92 _net123 'Rfeed*1'
RR4 0 _net92 910
RR5 _net93 _net92 10
RR6 _net88 _net93 50
VSRC1 _net94 0 3
RTerm2 Vout 0 50
xX1 vlow 0 vhigh 0 ATF55143
.ends circuit

These are netlist of SPICE syntax.

You have to convert these to ADSsim syntax or Cadence Spectre Syntax.
ADSsim can understand ADSsim syntax or Cadence Spectre Syntax directly.
ADSsim can not understand SPICE netlist.

See the followings.
http://www.designers-guide.org/Forum...1171334993/1#1
http://edocs.soco.agilent.com/displa...CE+and+Spectre
https://www.edaboard.com/viewtopic.php?t=370016

I think you use HSPICE from ADS framework not ADSsim as simulator.
http://edocs.soco.agilent.com/displa...+Compatibility

Since the netlist is inclomplete here is the netlist translator log:

Code:

Netlist Translator (*) 330.200 Nov  3 2007
ADS Netlist translation log

Input format: HSPICE
Input filename: C:\users\trial_prj\netlist.cnex

Output format: ADS Netlist file
Output filename: C:\Documents\atf55143.net

Special options:
    Processing first line as comment.

Begin translation at Mon Feb 22 12:34:36 2010

Creating netlist.
Reading item definition file "C:\ADS2008/config\spctoiff.cfg"
WARNING: Model "mesfetm1" for device "jfet1" in circuit "atf55143" not found.
Subcircuits found in Spice Netlist:   2
Subcircuits written to ADS Netlist:   2
Translation completed at Mon Feb 22 12:34:36 2010.

and here is the translated netlist:

Code:

; Translated with ADS Netlist Translator (*) 330.200 Nov  3 2007
; Design Name: circuit

; Date:        February 22, 2010 12:28:10
define atf55143 ( g s1 d s2)
 k=5
 z1=30
 z2=85

C:cc1 g s1 C=0.143p
C:cc2 d s1 C=0.115p
mesfetm1:jfet1 _net403 _net413 _net409 Mode=1
L:ll1 g _net413 L=0.621n
L:ll4 s1 _net409 L=0.238n
L:ll6 _net409 s1 L=0.205n
L:ll7 _net403 d L=0.778n
end atf55143

define circuit ()
 pavg=10

 rfeed=5100

C:cc1 0 _net94 C=10000p
C:cc2 0 _net123 C=8.2p
C:cc3 0 _net93 C=10000p
C:cc4 0 _net88 C=8.2p
C:cc5 vlow vin C=5.6p
C:cc6 vout _net121 C=2.2p
L:ll1 _net121 _net123 L=10n
L:ll2 _net106 _net121 L=5.6n
L:ll3 vlow _net88 L=2.7n
R:rr1 _net123 _net94 R=18
R:rr2 vhigh _net106 R=15
R:rr3 _net92 _net123 R=rfeed*1
R:rr4 0 _net92 R=910
R:rr5 _net93 _net92 R=10
R:rr6 _net88 _net93 R=50
V_Source:vsrc1 _net94 0 Vdc=3
R:rterm2 vout 0 R=50
atf55143:xx1 vlow 0 vhigh 0
end circuit

Do you have an idea why it doesnt include the transmission lines and the model definition?
Here is the main circuit as well.

If you use ADS correctly, transmission lines and the model definition are included naturally.

Why is "Netlist Translator" launched for your schematic ?
How did you generate netlist ?

If you use "ADS Netlist Exporter", it is not proper for simulation.
http://edocs.soco.agilent.com/displa...tlist+Exporter

Do netlisting by any method in the following.
http://www.designers-guide.org/Forum...1265191125/7#7

As far as I see both "circuit.JPG" and ""trans.JPG", you use only ADS native components in schematics.
So if you use ADS correctly, "Netlist Translator" can be never launched.

Surely read all my comments including refered links.

Sorry for my late reply, but thanks a lot! I finally figured out and finished my project! I was just not extracting the circuit netlist correctly...
Thanks so much!

hi all
I need help! I simulated a netlist file and I generated a *ds file for result from command window. I don't know how to generate for example a text file from this file for exporting s parameters from the command window.(I am using windows command prompt)

I can't understand what you want to do.

Windows command "dsdump" or AEL function "write_snp()" might be useful.
"write_snp()" can be included in netlist, if you put "Meas" component writing "write_snp()" in schematic.
Here yo don't have to create dds file to write "write_snp()".

https://www.edaboard.com/viewtopic.php?t=370016
https://www.edaboard.com/viewtopic.php?t=392510
http://edocs.soco.agilent.com/displa...rite+snp%28%29

Thanks Pancho. is it possible to do the same analysis using mumentum of ADS. I mean is there any file that can easily be run from command line?

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