- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
vco uhf ads
my vco:
.3.3v source voltage,0.18u SMIC's library
.useing complementary cross-coupled pair
.useing pmos to provide tail current
---all the mosfets are rf-moses
Wn:Wp=1:4 according to Un:Up
.useing outside chip LC-tank
---varactors : infineon bb659c
---inductor :RF wirewound inductor chip L->18n,R->0.22
I'm a unexperienced student in IC design. I've tried my every poor effort
(changing W/L& changing tail current), but the phase noise performance is
still not acceptable(-85db, my VCO rarely reach this standard is all the wave band).
I guess the Q value of the LC-tank is too high that the vco is easily
drived to voltage limit region. Maybe I should minish the W/L of the moses
which provid negative resistance, but smic have no narrower rf mosfets.
My guess is reasonable? Can you give me some good idea to optimize this
VCO? Giving a specific methods in optimization will be very appreciated. Thank U!
PS:
smic availiable rf mosfets:
3.3v fingerwidth channellength fingernumber
nmos 10u 0.35~0.5 8~24(even)
pmos 10u 0.35~0.5 8~24(even)
nmos 5u 0.35 12~32(even)
pmos 5u 0.35 12~32(even)
no replies -_-!
Have I asked a stupid qestion or I asked this qestion in a stupid way?
"Q value of the LC-tank is too high "
You should study the effect of Q on oscillator phase noise. There are some easy to understand papers written by Leeson. If your phase noise is too poor, you need a HIGHER Q.
I don't think so.
My condition is an extreme one, for a normal oscillator Q value is several dozens, and mine is several hundred. High Q means a high equivalent res, which means a lower current for a fixed output swing. And that will mean a smaller w/l-->higher 1/f noise
Thanks!
You mentioned -85 dB (I think you want to say -85 dBc), but at which offset?
Are you facing with flicker noise (close in, ~-30 dB/dec) or thermal one (far from carrier, ~-20 dB/dec)?
Mazz
How do you connect the off-chip inductor to your chip? Poor connections increase the resistance and degrade the Q
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