Cmos LNA Design Example in AWR

I want to design a cmos LNA circuit in AWR. I built in AWr and run.But I can't obtain reasonable result. I think I can't choose the right element.Could someone give me an example circuit,Please?

What kind of LNA ?
Frequency, Gain, Linearity, Noise Level, Wideband/Narrowband, Topology, Process etc. etc... ?

Please don't ask such questions that carry any information at all...

Sorry, I wrote this informations the previous post. So,I couldn't think that. I used 180nm Cmos process and apply the folded cascode LNA with Mds Technique (modified derivative superposition). The center frequency is 5GHz. I import the spice netlist in Awr, Level 49. I obtain some values but the gain is very odd. So I think that all circuit is wrong. (S21(gain)=-2.798dBm,S11=-11,355dBm,S22=-20.21dBm,Noise figure=2.278dBm,IIP3=12.76dBm).These are my results.

S-Parameters are not defined being as "dBm".
Your results are really unaccepable, there should be a biasing or matching errors or something else.It's you who will correct these results.
There also might be a importing netlist errors while translating into AWR because AWR interprets this netlist in according with its own netlisting procedure.Drawing the circuit again onto AWR will give you an insight.

Sorry, I wrote these accidentally. S11,S22 and S21 are dB. Do you have any circuit example. If you will give me an example circuit,I can compare with mine.

My Cmos LNA circuit's has an LC tank. I don't know which element should I use for inductor and capacitor. For capacitor can I use varactor? And If I can use a vcap, how can I import the data file of vcap?