怎么导入STDCELL的CDL

大家好！
我手头有standard cell的cadence symbol和cmos_sch view，但cmos_sch只有pin没有电路。
fab也提供了cdl文件，但我该如何把它导进去呢?
我在CDL IN页面填写了Reference Lib为analogLib，Device-Map file是自己写的，只有nfet和pfet。
请问大家是怎么做的?

我在CDL IN页面填写了Reference Lib为analogLib，Device-Map file是自己写的，只有nfet和pfet。
==>1. no connect line ?
     2. Reference Lib needs to have your process ex: XXX_018um
mpig

    Hi mpig,
1. What is connect line in map file? Can you provide an example?
2. May be the process is incomplete, it's not provided by foundry and from elsewhere. I just use it for study purpose.

Hi abcn101:
1. What is connect line in map file? Can you provide an example?
==>not in map file
       can you provide the schematic when your cdlin, and check the mos has connection line or not?
2. May be the process is incomplete, it's not provided by foundry and from elsewhere. I just use it for study purpose.
==>does the schematic has mos and the mos characteristic (w/l, type) is the same with your cdl?
mpig

关注这个问题- -我最近也要搞

    It does have connect line and mos, the size is correct too.
    But some input has become output and output has become input, in schematic view.
   For example A is input in symbol but became output in sch,
   Y is output in symbol but became input in sch.

Hi abcn101:
It does have connect line and mos, the size is correct too.
    But some input has become output and output has become input, in schematic view.
   For example A is input in symbol but became output in sch,
   Y is output in symbol but became input in sch.
==>Sorry, I don't know how to solve this problem.
      I solve it manually.
Hope someone know how to solve it.
mpig

   为什么Device Map File中要写nfet和pfet?是因为你用的是analogLib吗?
如果我把reference Lib设定为PDK，那应该怎么办?

    我也就看到网上怎么说的，
PDK的情况就不清楚了

   OK 3Q！

我也遇到和小编相似的问题，一是CDL导入不成功，二是symbol和schematic的port对不上
帮顶，同求解答。小编方便的话可以一起讨论

  对不上可以自己改啊

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