hspice rf的高手们帮帮我吧(mixer设计)
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小弟本科毕设做得是一个吉尔伯特混频器,想得到它的1-db压缩点,开关级lo为理想方波信号,输入rf信号进行功率扫描,从-50dbm到0,hspicerf manual中有相关的例子,不过是单端输入的,现在rf信号是双端输入,利用.hb分析法,我怎么也仿真不出来.hb文件,高手帮我指点一下其中的问题所在吧
*traditional gilbet mixer
.LIB `.\mm018.l` TT
.param flo=2.2g frf=2.4g
.param l=0.18u w=50u
.param t=1/flo
.param prf:dbm=-30
.param prf=prf:dbm
.param prf:w='1.0e-3*pwr(10.0,Prf/10.0)'
m1 d1 g1 s1 s1 NCH l w
m2 d2 g2 s1 s1 NCH l w
m3 d3 g3 d1 d1 NCH l w
m4 d6 g4 d1 d1 NCH l w
m5 d3 g4 d2 d2 NCH l w
m6 d6 g3 d2 d2 NCH l w
rload1 vdd d3 1k
rload2 vdd d6 1k
Iss s1 gnd 200uA
lchk1 g1 bias1 INFINITY $choke
cblk1 g1 in1 INFINITY $ DC block
lchk2 g2 bias2 INFINITY $choke
cblk2 g2 in2 INFINITY $ DC block
vbias1 bias1 gnd dc=1.0
vbias2 bias2 gnd dc=1.0
vrf1 in1 gnd dc=0 power=1 z0=50 hb prf:w 0 1 1
vrf2 in2 gnd dc=0 power=1 z0=50 hb prf:w 180 1 1
vlo1 g3 gnd PULSE 0 1 0.5*t 0 0 0.5*t t
vlo2 g4 gnd PULSE -1 0 0.5*t 0 0 0.5*t t
.HB tones=frf nharms=10
+ sweep prf:dbm -50 0 2.0
vdd vdd gnd DC 3.3
.probe hb v(d3,d6)
.print HB outputpower=par('p(rload1)+p(rload2)')
.probe HB outputpower=par('p(rload1)+p(rload2)')
.end
*traditional gilbet mixer
.LIB `.\mm018.l` TT
.param flo=2.2g frf=2.4g
.param l=0.18u w=50u
.param t=1/flo
.param prf:dbm=-30
.param prf=prf:dbm
.param prf:w='1.0e-3*pwr(10.0,Prf/10.0)'
m1 d1 g1 s1 s1 NCH l w
m2 d2 g2 s1 s1 NCH l w
m3 d3 g3 d1 d1 NCH l w
m4 d6 g4 d1 d1 NCH l w
m5 d3 g4 d2 d2 NCH l w
m6 d6 g3 d2 d2 NCH l w
rload1 vdd d3 1k
rload2 vdd d6 1k
Iss s1 gnd 200uA
lchk1 g1 bias1 INFINITY $choke
cblk1 g1 in1 INFINITY $ DC block
lchk2 g2 bias2 INFINITY $choke
cblk2 g2 in2 INFINITY $ DC block
vbias1 bias1 gnd dc=1.0
vbias2 bias2 gnd dc=1.0
vrf1 in1 gnd dc=0 power=1 z0=50 hb prf:w 0 1 1
vrf2 in2 gnd dc=0 power=1 z0=50 hb prf:w 180 1 1
vlo1 g3 gnd PULSE 0 1 0.5*t 0 0 0.5*t t
vlo2 g4 gnd PULSE -1 0 0.5*t 0 0 0.5*t t
.HB tones=frf nharms=10
+ sweep prf:dbm -50 0 2.0
vdd vdd gnd DC 3.3
.probe hb v(d3,d6)
.print HB outputpower=par('p(rload1)+p(rload2)')
.probe HB outputpower=par('p(rload1)+p(rload2)')
.end
顶起啊
first do DC and tran simulation make sure the transistors behaves as you expected
可以自己用verilog-a写一个单转双的balun
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