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protel99编译GAL
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protel99编译GAL器件,编译成功,仿真波形也对,但是生成的JED文件烧到片子上,逻辑关系不对,求高手指导。
我要烧写的目标器件为 GAL16V8D,程序如下:
Name PLDDesign ;
Partno ;
Revision 1 ;
Date 2011-6-8 ;
Designer ;
Company Protel International ;
Assembly ;
Location ;
Device g16v8 ;
Format J ;
/*********************************************************************/
/* This PLD design (Revision 1) created on 2011-6-8 */
/* for Protel International */
/* and is stored as PLDDesign */
/*********************************************************************/
/** Inputs **/
Pin 1 = CLK;
Pin 2 = PS ;
Pin 3 = RD ;
Pin 4 = I3 ;
Pin 5 = I4;
Pin 6 = FTMS ;
Pin 7 = TCK ;
Pin 8 = FTDI ;
Pin 9 = TDO ;
Pin 10 = GND;
/** Outputs **/
Pin 11 = OE;
Pin 12 = OUCE;
Pin 13 = OU13;
Pin 14 = OU14;
Pin 15 = OU15;
Pin 16 = STDO;
Pin 17 = TDI;
Pin 18 = STCK;
Pin 19 = TMS;
Pin 20 = VCC;
/** Declarations and Intermediate Variables **/
/** Logic Equations **/
TMS = FTMS;
STCK = TCK;
TDI = FTDI;
STDO =TDO;
OUCE = PS# RD;
我要烧写的目标器件为 GAL16V8D,程序如下:
Name PLDDesign ;
Partno ;
Revision 1 ;
Date 2011-6-8 ;
Designer ;
Company Protel International ;
Assembly ;
Location ;
Device g16v8 ;
Format J ;
/*********************************************************************/
/* This PLD design (Revision 1) created on 2011-6-8 */
/* for Protel International */
/* and is stored as PLDDesign */
/*********************************************************************/
/** Inputs **/
Pin 1 = CLK;
Pin 2 = PS ;
Pin 3 = RD ;
Pin 4 = I3 ;
Pin 5 = I4;
Pin 6 = FTMS ;
Pin 7 = TCK ;
Pin 8 = FTDI ;
Pin 9 = TDO ;
Pin 10 = GND;
/** Outputs **/
Pin 11 = OE;
Pin 12 = OUCE;
Pin 13 = OU13;
Pin 14 = OU14;
Pin 15 = OU15;
Pin 16 = STDO;
Pin 17 = TDI;
Pin 18 = STCK;
Pin 19 = TMS;
Pin 20 = VCC;
/** Declarations and Intermediate Variables **/
/** Logic Equations **/
TMS = FTMS;
STCK = TCK;
TDI = FTDI;
STDO =TDO;
OUCE = PS# RD;
这个有点难.我没有做过.纯属顶贴.希望高手来解答.
谢谢,我已经解决了,原来是片子本身有问题,换了一个芯片就好了。
我用原理图设计16V8老是编译不成功
各位大侠能教教我怎么用原理图设计GAL吗
最好是图文并茂的
谢谢啦
Cadence Allegro 培训套装,视频教学,直观易学
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