- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
AD6.7的增加功能说明2
录入：edatop.com 点击：
31. Pin swapping has been improved. Previously, if any component was not linked to a schematic
component, pin swapping was disabled. Now it is possible to use pin swapping for linked
components, ignoring unlinked components.
32. Gerber Extension and Layer Name have been added to Gerber / ODB++ Setup dialog for
single board output.
© 2006 Altium Limited Page 3 of 10
33. Board level libraries have been added for Stratix II GX devices.
34. New mode added to PCB panel which provides comprehensive navigation, filtering and editing
of drill hole information for PCB design objects.
35. Board level libraries have been added for Xilinx Spartan3L devices.
36. The report generator for the IPC Footprint Wizard batch mode now includes all errors and
warnings in the report, and a potential memory leak was also fixed.
37. Board level libraries have been added for Lattice ECP2/M devices.
38. Snippets in PCB room
definitions were not placed properly: This has been fixed. It is now
possible to place rooms from snippets.
39. Impedance driven Width Rule rounding problems: Improved rounding accuracy for impedance
driven rules when switching between imperial and metric units.
40. Mismatched layer names in Hyperlynx Export: The Hyperlynx Exporter has been improved.
Layer names are now consistent throughout the exported hyperlynx files.
41. Phantom electric snap when moving selection: The Move Selection command has been
improved. The electric grid no longer snaps to objects in the selection.
42. A duplicate "L" hotkey
has been removed from the PCB Tools Menu.
43. The Rounded Rectangular pads corner radius field will now be exported when generating a
PCB Library from a PCB document.
44. Gerber and ODB++ generation for embedded board arrays has been improved; now
embedded boards with different layers in their layer stacks will be exported correctly.
45. The "Test DirectX..." button has been fixed to work, even when there is no PCB document
open.
46. Three new buttons have been added to the PCB Show/Hide preferences enabling quick
manipulation of the Final/Draft drawing mode status of visible primitives.
47. SPECCTRA Make
restoring shelved polygons optional. This applies when exporting to DSN
shelved polygons as they will not be restored before you export.
48. Find Test Points: Improved behavior of the “find test points process” has been implemented.
49. Shelve Polygon options now appear on the right click context menu (when user's cursor is
focused on polygon object).
50. Increased minimum component grid resolution from 5mil (0.127mm) to 1mil (0.0254mm) previously
it was not possible to move components to 0.1mm grid.
51. No longer will the'" is not a valid integer value" messages appear when an invalid value is
entered. Now the control will reset it to 0.
52. The “touches room function” has been rectified to work correctly on small overlaps on the top
edge of a rectangular room.
53. Now the slots in embedded boards will export to NC Drill with the correct rotation if the
embedded board is rotated.
54. Printouts use to have pre 6.6 drill legend instead of new table format, this has been fixed.
Printouts now use the new drill legend table.
55. The IPC Footprint Wizard QFN package now supports two different pitches ie one vertically
and one horizontally.
56. DSN Importer: Updated SPECCTRA DSN file format importer now supports new format
revisions ie Allegro produced support files.
57. Gerber files: Gerber files that contain arcs will be correctly generated all the time. Prior to this
change some arcs could've been exported as counterclockwise
(G03) even if the ends shown
them to be clockwise (G02).
© 2006 Altium Limited Page 4 of 10
58. Components that contain bitmap references are now correctly saved in PCB3d library files.
59. Reuse drill symbols for same drill sizes on all legends. Now the drill symbols will be reused
when blind and buried vias are present in the design.
60. Solid polygon pouring around fills follows clearance more correctly using rounded outlining.
61. The corner radius for rounded rectangular pad shapes can now be changed using the
Inspector and List Panels. This is similar to all the other pad's properties.
62. The Size of the hole string symbols in the drill legend is now correct. The DrillDrawing Legend
will display the correct Symbol when the HoleSize String Symbols is used.
63. Single Layer Mode can now be controlled separately for PCB and PCB Library using new
combo box control on the Board Insight Display Preferences.
64. Copying footprints with the same name between open PCB libraries will now use the correct
footprint instance instead of the first found footprint.
65. Slice Tracks feature update: In the PCB Editor, any tracks that belong to a component that are
locked or the component itself is locked, will no longer be sliced. Please note: In the PCB
Library Editor the current behavior will be maintained.
66. Embedded Board Array display: The DirectX graphics mode has been improved. Embedded
board arrays are now drawn in front of the defined board area.
67. Implement dragging of arcs whilst maintaining connectivity: Arcs can now be dragged while
conserving the configuration of connected tracks. This is a new behavior that operates with
the Preserve Angle When Dragging option checked in Interactive Routing Preferences. When
you select and drag at the mid handle of an arc that is tangentially connected to tracks at one
or both ends, the arc is dragged in a manner that maintains connectivity with its adjacent
tracks.
68. AntiPads
were not exporting correctly to ODB++ when slot holes are used: This has now
been rectified; the antipads
(voids) on internal plane layers will export correctly to ODB++
when slot holes are used.
69. Polygon cutouts to apply to polygons on non signal layers: Polygons placed on non signal
layers will now obey cutout objects allowing more complex shape definitions on mechanical
and overlay layers.
70. Component (CMP) records in ODB++ where previously missing part name. This has been
fixed: the component records in the ODB++ component files will now contain the <part_name>
= Component Comment (instead of the '?'). The comment should be unique and is used in
the BOM to group the components so it actually behaves like a part_name. In addition, if the
Comment contains spaces, these spaces will be replaced with '_' because Valor can not
handle spaces in string literals.
71. SPECCTRA – would previously not run update free primitives when importing RTE File. After
importing RTE File from SPECCTRA electrical primitives will no longer be updated from
component pads, preserving their net assignments from SPECCTRA.
72. Missing micro vias in ODB++ output. There should be no missing vias in ODB++ drill files
export if the vias have reversed start and stop layers.
73. Unions containing locked components could move without warning. Now a union that contains
locked components will not be able to be moved. A message dialog will popup
asking if the
user wants to move the union regardless.
74. The PCB3D viewer has been improved in its support for different pad shapes. The viewer
supports the rounded rectangular shape as well as the square and slot holes.
75. Background color for pcb3dlib. The background color was not working for pcb3dlib. This has
been fixed.
76. ODB++ eda/data file now contains the net $NONE$ as the first defined net including all
objects that have no net assigned to them.
© 2006 Altium Limited Page 5 of 10
77. DXP hangs when deleting excessive number of primitives from Undo Stack: Large entries in
the Undo stack no longer cause delays when the undo limit is reached.
78. The stability of the undo system has been improved. Previously undo a delete operation had
some potential to cause crashes at a later point in time.
79. Pouring a solid polygon over a multilayer pad with no land or hole size on the polygons layers
no longer causes a void in the polygon.
80. Power Plane connection style now defaults to "No Connect" when no connect style rule is
applicable to a pad or via. This behavior is now consistent with Gerber generation. Previously
it was possible to have a clean DRC, but generate Gerber with connectivity problems due to
plane isolations.
Schematic
1. A rare crash in Schematic on Altium Designer exit has been fixed. It no longer crashes when
closing Altium Designer.
2. Port Cross Reference redrawing has been fixed. Port Cross References now display correctly
in the schematic editor as the view changes.
3. Schematics have been improved. Designators can now be set so that they can be manually
positioned.
4. During pin placement in Schematics an option has been provided that will allow the autoincrement
feature to remove leading zeroes.
5. Unpredictable behavior while placing and modifying Bezier curves has been fixed.
6. Default primitives Permanent option: The Schematic component default is no longer modified
after dragndropping
a part from the library panel, when the Permanent option is set to ON.
7. The paste tool has been improved. Previously, any transformations on clipboard objects
during a paste operation were remembered in subsequent pastes. Now, subsequent paste
operations use only the original clipboard objects, preventing unexpected changes.
8. The use of the Y key when pasting has been improved. Now, when pasting or dragging a
selection of objects, the Y key will flip the objects including net labels with the correct
orientation.
9. The function of reference zones in the margins of a schematic sheet has been improved. With
"Show Reference Zones" turned off in the Document Options, the margins of the sheet now
behave as any other part of the sheet. This makes it possible to click and drag to select
objects at the border of the sheet.
10. The Schematic Inspector has been improved. Objects containing lots of parameters will no
longer crash the Inspector.
11. The redirection text for the variant name, '=VariantName', has been added to the list of
parameters in the text properties dialog.
12. Place graphic proportion
was occasionally incorrect when first placed, this has been rectified
and now when placing images on the schematic it respects settings in X:Y ratio.
13. Variant parameters are now supported in outputs. Add a variant parameter to 'Variant 1' (ie
Name='VarTitle', Value='Title for Variant1'). Place a redirected text string with the format
'=ParameterName' (ie '=VarTitle'). At output, the parameter's value for the selected variant will
be displayed (ie 'Title for Variant1').
14. Standard ASME Y14.1, calls for zone indicators to be alpha on the sides starting from the
bottom working upwards numeric
on the top and bottom starting from the right to left. This
update allows these zones to be specified in the template. Ensure the Port Cross Reference
features work with the zones. Support has been added for the ASME Y14.1 sheet reference
© 2006 Altium Limited Page 6 of 10
zone standard. In the Document Options dialog, make sure 'Show Reference Zones' is
checked. From the drop down list below the check box, choose a reference zone style.
15. Schematic documents with rotated dot symbols can now be opened.
16. In the past, Altium Design will crash upon exit after importing PCAD
library file. This has
been fixed.
FPGA
1. An automatically generated SDC file is no longer contains a comma as the decimal point for
clock constraints. Commas were causing the constraints to be ignored by Actel while using
non English language settings in Windows.
2. DSF drivers have been included for the WB_UART8 core.
3. Support for Altera Cyclone III devices has been added.
4. Support for Lattice ispLEVER 6.1 has been added.
5. Selecting an Altera Lead Free device is no longer causing the Build stage of the FPGA flow to
fail with an Illegal Part Name error.
6. QuartusII and NiosII v6.1 Support: Support for Altera QuartusII and NiosII has been added.
7. Add JTAG sequences for Cyclone2 devices: Programming Altera Cyclone2 devices is no
longer causing the "Failed to program device" dialog to popup after checking the
Config_Done.
8. Default comment identifier for Altera TCLQ constraint file has been corrected.
9. Exception in CoreGenerator.Dll when synthesizing: Synthesis process for Actel cores has
been improved to address an exception in the CoreGenerator module.
10. The document CR0122 EMACx Controller.pdf has been updated to fix incorrect register
address representation. These addresses are now in true hex representation. Additional
information has also been added for buffer and Controller initialization.
11. The Default Options button in the Error Reporting tab in the ProjectOptions for FPGA/CORE
projects now sets all the error conditions to their correct default values.
12. It's now possible (added as an option called "Import All Signals") to include signals from a
constraint file that are not part of the project. Previously the only way to do this was to open
the constraint file outside of the project and do the import.
13. Mixed design (VHDL and Verilog) projects should now work properly when using XST as the
synthesizer. Also search paths are now properly passed on for Verilog files.
14. Support for Spartan3A devices have been added.
15. Actel Designer 7.2 SP1 and SP2 are now supported.
16. A new core Importer Wizard has been added to assist in using thirdparty
models from FPGA
Vendor tools such as Xilinx's CoreGen or Altera's Megawizard. Just run the respective tools
as standalone and then invoke the wizard via Tools >
FPGA ThirdParty
IP Import to use it in
your FPGA project.
17. Programming support for Stratix II GX: Support for Stratix II GX devices has been added.
18. Programming support for Spartan3L: Support for Xilinx Spartan3L devices has been added.
19. Support for Xilinx ISE 9.1i has been added.
20. Programming support for ECP2/M: Support for ECP2/M devices has been added.
21. Third Party Vendor Tools Options has been upgraded to now support more options for all the
vendors. There is now a feature to show/hide more advanced options.
© 2006 Altium Limited Page 7 of 10
SystemLevel
1. Advanced line numbers in the text editor: The text editor can now show numbers not for all
lines but for every 10th one and for the current one. This significantly reduces information
pollution and helps the eye to catch the crucial information.
2. A bug in the library panel has been fixed. An error that could occur when hiding the library
panel after performing a library search has been fixed.
3. The library queries have been improved. A bug that raised an access violation when clicking
'Edit PCB3D Model' or 'Edit Component' from the query results has been fixed.
4. Sometimes the 2 Grids on the same form with Registry Path don't store themselves correctly
and overwrite each other. This has now been fixed.
5. Now if users close a HTML document from Free Projects it will always be correctly removed
from Free Projects.
6. Now Font Dialog always appears on screen with an active window.
7. The SVN revision list now shows all revisions for files instead of only the revisions up until the
checked out revision.
component, pin swapping was disabled. Now it is possible to use pin swapping for linked
components, ignoring unlinked components.
32. Gerber Extension and Layer Name have been added to Gerber / ODB++ Setup dialog for
single board output.
© 2006 Altium Limited Page 3 of 10
33. Board level libraries have been added for Stratix II GX devices.
34. New mode added to PCB panel which provides comprehensive navigation, filtering and editing
of drill hole information for PCB design objects.
35. Board level libraries have been added for Xilinx Spartan3L devices.
36. The report generator for the IPC Footprint Wizard batch mode now includes all errors and
warnings in the report, and a potential memory leak was also fixed.
37. Board level libraries have been added for Lattice ECP2/M devices.
38. Snippets in PCB room
definitions were not placed properly: This has been fixed. It is now
possible to place rooms from snippets.
39. Impedance driven Width Rule rounding problems: Improved rounding accuracy for impedance
driven rules when switching between imperial and metric units.
40. Mismatched layer names in Hyperlynx Export: The Hyperlynx Exporter has been improved.
Layer names are now consistent throughout the exported hyperlynx files.
41. Phantom electric snap when moving selection: The Move Selection command has been
improved. The electric grid no longer snaps to objects in the selection.
42. A duplicate "L" hotkey
has been removed from the PCB Tools Menu.
43. The Rounded Rectangular pads corner radius field will now be exported when generating a
PCB Library from a PCB document.
44. Gerber and ODB++ generation for embedded board arrays has been improved; now
embedded boards with different layers in their layer stacks will be exported correctly.
45. The "Test DirectX..." button has been fixed to work, even when there is no PCB document
open.
46. Three new buttons have been added to the PCB Show/Hide preferences enabling quick
manipulation of the Final/Draft drawing mode status of visible primitives.
47. SPECCTRA Make
restoring shelved polygons optional. This applies when exporting to DSN
shelved polygons as they will not be restored before you export.
48. Find Test Points: Improved behavior of the “find test points process” has been implemented.
49. Shelve Polygon options now appear on the right click context menu (when user's cursor is
focused on polygon object).
50. Increased minimum component grid resolution from 5mil (0.127mm) to 1mil (0.0254mm) previously
it was not possible to move components to 0.1mm grid.
51. No longer will the'" is not a valid integer value" messages appear when an invalid value is
entered. Now the control will reset it to 0.
52. The “touches room function” has been rectified to work correctly on small overlaps on the top
edge of a rectangular room.
53. Now the slots in embedded boards will export to NC Drill with the correct rotation if the
embedded board is rotated.
54. Printouts use to have pre 6.6 drill legend instead of new table format, this has been fixed.
Printouts now use the new drill legend table.
55. The IPC Footprint Wizard QFN package now supports two different pitches ie one vertically
and one horizontally.
56. DSN Importer: Updated SPECCTRA DSN file format importer now supports new format
revisions ie Allegro produced support files.
57. Gerber files: Gerber files that contain arcs will be correctly generated all the time. Prior to this
change some arcs could've been exported as counterclockwise
(G03) even if the ends shown
them to be clockwise (G02).
© 2006 Altium Limited Page 4 of 10
58. Components that contain bitmap references are now correctly saved in PCB3d library files.
59. Reuse drill symbols for same drill sizes on all legends. Now the drill symbols will be reused
when blind and buried vias are present in the design.
60. Solid polygon pouring around fills follows clearance more correctly using rounded outlining.
61. The corner radius for rounded rectangular pad shapes can now be changed using the
Inspector and List Panels. This is similar to all the other pad's properties.
62. The Size of the hole string symbols in the drill legend is now correct. The DrillDrawing Legend
will display the correct Symbol when the HoleSize String Symbols is used.
63. Single Layer Mode can now be controlled separately for PCB and PCB Library using new
combo box control on the Board Insight Display Preferences.
64. Copying footprints with the same name between open PCB libraries will now use the correct
footprint instance instead of the first found footprint.
65. Slice Tracks feature update: In the PCB Editor, any tracks that belong to a component that are
locked or the component itself is locked, will no longer be sliced. Please note: In the PCB
Library Editor the current behavior will be maintained.
66. Embedded Board Array display: The DirectX graphics mode has been improved. Embedded
board arrays are now drawn in front of the defined board area.
67. Implement dragging of arcs whilst maintaining connectivity: Arcs can now be dragged while
conserving the configuration of connected tracks. This is a new behavior that operates with
the Preserve Angle When Dragging option checked in Interactive Routing Preferences. When
you select and drag at the mid handle of an arc that is tangentially connected to tracks at one
or both ends, the arc is dragged in a manner that maintains connectivity with its adjacent
tracks.
68. AntiPads
were not exporting correctly to ODB++ when slot holes are used: This has now
been rectified; the antipads
(voids) on internal plane layers will export correctly to ODB++
when slot holes are used.
69. Polygon cutouts to apply to polygons on non signal layers: Polygons placed on non signal
layers will now obey cutout objects allowing more complex shape definitions on mechanical
and overlay layers.
70. Component (CMP) records in ODB++ where previously missing part name. This has been
fixed: the component records in the ODB++ component files will now contain the <part_name>
= Component Comment (instead of the '?'). The comment should be unique and is used in
the BOM to group the components so it actually behaves like a part_name. In addition, if the
Comment contains spaces, these spaces will be replaced with '_' because Valor can not
handle spaces in string literals.
71. SPECCTRA – would previously not run update free primitives when importing RTE File. After
importing RTE File from SPECCTRA electrical primitives will no longer be updated from
component pads, preserving their net assignments from SPECCTRA.
72. Missing micro vias in ODB++ output. There should be no missing vias in ODB++ drill files
export if the vias have reversed start and stop layers.
73. Unions containing locked components could move without warning. Now a union that contains
locked components will not be able to be moved. A message dialog will popup
asking if the
user wants to move the union regardless.
74. The PCB3D viewer has been improved in its support for different pad shapes. The viewer
supports the rounded rectangular shape as well as the square and slot holes.
75. Background color for pcb3dlib. The background color was not working for pcb3dlib. This has
been fixed.
76. ODB++ eda/data file now contains the net $NONE$ as the first defined net including all
objects that have no net assigned to them.
© 2006 Altium Limited Page 5 of 10
77. DXP hangs when deleting excessive number of primitives from Undo Stack: Large entries in
the Undo stack no longer cause delays when the undo limit is reached.
78. The stability of the undo system has been improved. Previously undo a delete operation had
some potential to cause crashes at a later point in time.
79. Pouring a solid polygon over a multilayer pad with no land or hole size on the polygons layers
no longer causes a void in the polygon.
80. Power Plane connection style now defaults to "No Connect" when no connect style rule is
applicable to a pad or via. This behavior is now consistent with Gerber generation. Previously
it was possible to have a clean DRC, but generate Gerber with connectivity problems due to
plane isolations.
Schematic
1. A rare crash in Schematic on Altium Designer exit has been fixed. It no longer crashes when
closing Altium Designer.
2. Port Cross Reference redrawing has been fixed. Port Cross References now display correctly
in the schematic editor as the view changes.
3. Schematics have been improved. Designators can now be set so that they can be manually
positioned.
4. During pin placement in Schematics an option has been provided that will allow the autoincrement
feature to remove leading zeroes.
5. Unpredictable behavior while placing and modifying Bezier curves has been fixed.
6. Default primitives Permanent option: The Schematic component default is no longer modified
after dragndropping
a part from the library panel, when the Permanent option is set to ON.
7. The paste tool has been improved. Previously, any transformations on clipboard objects
during a paste operation were remembered in subsequent pastes. Now, subsequent paste
operations use only the original clipboard objects, preventing unexpected changes.
8. The use of the Y key when pasting has been improved. Now, when pasting or dragging a
selection of objects, the Y key will flip the objects including net labels with the correct
orientation.
9. The function of reference zones in the margins of a schematic sheet has been improved. With
"Show Reference Zones" turned off in the Document Options, the margins of the sheet now
behave as any other part of the sheet. This makes it possible to click and drag to select
objects at the border of the sheet.
10. The Schematic Inspector has been improved. Objects containing lots of parameters will no
longer crash the Inspector.
11. The redirection text for the variant name, '=VariantName', has been added to the list of
parameters in the text properties dialog.
12. Place graphic proportion
was occasionally incorrect when first placed, this has been rectified
and now when placing images on the schematic it respects settings in X:Y ratio.
13. Variant parameters are now supported in outputs. Add a variant parameter to 'Variant 1' (ie
Name='VarTitle', Value='Title for Variant1'). Place a redirected text string with the format
'=ParameterName' (ie '=VarTitle'). At output, the parameter's value for the selected variant will
be displayed (ie 'Title for Variant1').
14. Standard ASME Y14.1, calls for zone indicators to be alpha on the sides starting from the
bottom working upwards numeric
on the top and bottom starting from the right to left. This
update allows these zones to be specified in the template. Ensure the Port Cross Reference
features work with the zones. Support has been added for the ASME Y14.1 sheet reference
© 2006 Altium Limited Page 6 of 10
zone standard. In the Document Options dialog, make sure 'Show Reference Zones' is
checked. From the drop down list below the check box, choose a reference zone style.
15. Schematic documents with rotated dot symbols can now be opened.
16. In the past, Altium Design will crash upon exit after importing PCAD
library file. This has
been fixed.
FPGA
1. An automatically generated SDC file is no longer contains a comma as the decimal point for
clock constraints. Commas were causing the constraints to be ignored by Actel while using
non English language settings in Windows.
2. DSF drivers have been included for the WB_UART8 core.
3. Support for Altera Cyclone III devices has been added.
4. Support for Lattice ispLEVER 6.1 has been added.
5. Selecting an Altera Lead Free device is no longer causing the Build stage of the FPGA flow to
fail with an Illegal Part Name error.
6. QuartusII and NiosII v6.1 Support: Support for Altera QuartusII and NiosII has been added.
7. Add JTAG sequences for Cyclone2 devices: Programming Altera Cyclone2 devices is no
longer causing the "Failed to program device" dialog to popup after checking the
Config_Done.
8. Default comment identifier for Altera TCLQ constraint file has been corrected.
9. Exception in CoreGenerator.Dll when synthesizing: Synthesis process for Actel cores has
been improved to address an exception in the CoreGenerator module.
10. The document CR0122 EMACx Controller.pdf has been updated to fix incorrect register
address representation. These addresses are now in true hex representation. Additional
information has also been added for buffer and Controller initialization.
11. The Default Options button in the Error Reporting tab in the ProjectOptions for FPGA/CORE
projects now sets all the error conditions to their correct default values.
12. It's now possible (added as an option called "Import All Signals") to include signals from a
constraint file that are not part of the project. Previously the only way to do this was to open
the constraint file outside of the project and do the import.
13. Mixed design (VHDL and Verilog) projects should now work properly when using XST as the
synthesizer. Also search paths are now properly passed on for Verilog files.
14. Support for Spartan3A devices have been added.
15. Actel Designer 7.2 SP1 and SP2 are now supported.
16. A new core Importer Wizard has been added to assist in using thirdparty
models from FPGA
Vendor tools such as Xilinx's CoreGen or Altera's Megawizard. Just run the respective tools
as standalone and then invoke the wizard via Tools >
FPGA ThirdParty
IP Import to use it in
your FPGA project.
17. Programming support for Stratix II GX: Support for Stratix II GX devices has been added.
18. Programming support for Spartan3L: Support for Xilinx Spartan3L devices has been added.
19. Support for Xilinx ISE 9.1i has been added.
20. Programming support for ECP2/M: Support for ECP2/M devices has been added.
21. Third Party Vendor Tools Options has been upgraded to now support more options for all the
vendors. There is now a feature to show/hide more advanced options.
© 2006 Altium Limited Page 7 of 10
SystemLevel
1. Advanced line numbers in the text editor: The text editor can now show numbers not for all
lines but for every 10th one and for the current one. This significantly reduces information
pollution and helps the eye to catch the crucial information.
2. A bug in the library panel has been fixed. An error that could occur when hiding the library
panel after performing a library search has been fixed.
3. The library queries have been improved. A bug that raised an access violation when clicking
'Edit PCB3D Model' or 'Edit Component' from the query results has been fixed.
4. Sometimes the 2 Grids on the same form with Registry Path don't store themselves correctly
and overwrite each other. This has now been fixed.
5. Now if users close a HTML document from Free Projects it will always be correctly removed
from Free Projects.
6. Now Font Dialog always appears on screen with an active window.
7. The SVN revision list now shows all revisions for files instead of only the revisions up until the
checked out revision.
