哪位帮我看看我的PCB的DRC报告，我是新手，不知道是什么意思，

这报告是不是显示有很多错误啊，我刚学Protel，什么都不懂，请好心人详细指点，万分感谢！

Protel Design System Design Rule Check
PCB File : Documents\AIC1610-2.PCB
Date     : 17-Jul-2007
Time     : 11:06:28

Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (On the board )
Rule Violations :0

Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (On the board )
   Violation         Track (587.81933mm,131.45101mm)(590.79013mm,131.45101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (594.10433mm,130.15101mm)(596.66133mm,127.59401mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (596.66133mm,124.03801mm)(599.20133mm,127.59401mm)  TopLayer  Actual Width = 0.5mm
   Violation         Track (593.37933mm,131.45101mm)(595.25947mm,131.45101mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (595.25947mm,131.45101mm)(595.59882mm,131.79036mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (595.59882mm,131.79036mm)(595.59882mm,139.85964mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (596.66133mm,127.59401mm)(596.66133mm,136.16751mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (596.66133mm,136.16751mm)(601.04628mm,140.55246mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (594.12133mm,122.01974mm)(594.12133mm,124.03801mm)  TopLayer  Actual Width = 0.5mm
   Violation         Track (594.12133mm,122.01974mm)(601.59292mm,122.01974mm)  TopLayer  Actual Width = 0.5mm
   Violation         Track (601.59292mm,122.01974mm)(601.59292mm,131.29842mm)  TopLayer  Actual Width = 0.5mm
   Violation         Track (599.20133mm,133.69001mm)(601.59292mm,131.29842mm)  TopLayer  Actual Width = 0.5mm
   Violation         Track (583.73933mm,130.80101mm)(587.81933mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (587.51733mm,136.99201mm)(587.51733mm,142.99908mm)  TopLayer  Actual Width = 1mm
   Violation         Track (587.51733mm,142.99908mm)(588.08652mm,143.56827mm)  TopLayer  Actual Width = 1mm
   Violation         Track (588.08652mm,143.56827mm)(602.64924mm,143.56827mm)  TopLayer  Actual Width = 1mm
   Violation         Track (602.64924mm,143.56827mm)(603.54585mm,142.67166mm)  TopLayer  Actual Width = 1mm
   Violation         Track (603.54585mm,138.03453mm)(603.54585mm,142.67166mm)  TopLayer  Actual Width = 1mm
   Violation         Track (599.20133mm,133.69001mm)(603.54585mm,138.03453mm)  TopLayer  Actual Width = 1mm
   Violation         Track (584.45087mm,134.70601mm)(587.51733mm,134.70601mm)  TopLayer  Actual Width = 1mm
   Violation         Track (582.57114mm,136.58574mm)(584.45087mm,134.70601mm)  TopLayer  Actual Width = 1mm
   Violation         Track (582.57114mm,136.58574mm)(582.57114mm,140.49813mm)  TopLayer  Actual Width = 1mm
   Violation         Track (588.91933mm,131.45101mm)(590.11933mm,131.45101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (583.62371mm,131.22741mm)(585.40627mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (583.72424mm,130.07292mm)(585.40627mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (583.57508mm,130.87896mm)(585.40627mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (583.61611mm,130.40772mm)(585.40627mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (583.58033mm,130.64201mm)(585.40627mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (585.51933mm,130.80101mm)(586.71933mm,130.80101mm)  TopLayer  Actual Width = 0.35mm
   Violation         Track (593.37933mm,130.15101mm)(595.13189mm,129.12345mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (587.51733mm,137.11901mm)(587.51733mm,140.75401mm)  TopLayer  Actual Width = 1mm
   Violation         Track (594.47933mm,131.45101mm)(595.25947mm,131.45101mm)  TopLayer  Actual Width = 0.3mm
   Violation         Track (582.57114mm,136.58574mm)(583.46517mm,140.39461mm)  TopLayer  Actual Width = 1mm
   Violation         Track (581.67711mm,140.39461mm)(582.57114mm,136.58574mm)  TopLayer  Actual Width = 1mm
   Violation         Track (595.59882mm,138.04369mm)(596.15555mm,140.58613mm)  TopLayer  Actual Width = 0.3mm
 .
 .（这里还有一大堆）
 .
 .

Rule Violations :500

Processing Rule : Clearance Constraint (Gap=0.254mm) (On the board ),(On the board )
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (On the board ) )
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0

More than 500 violations detected. DRC stopped！

Violations Detected : 501
Time Elapsed        : 00:00:01

线宽的问题，你设置下铺铜线的宽度
这个应该是铺铜线宽引起的问题

是你的线宽设置不对

Processing Rule : Width Constraint (Min=0.254mm) (Max=0.254mm) (Prefered=0.254mm) (On the board )
应该把Max=0.254mm 改大,如:Max=2.54mm,就可以了。

问题解决，真的十分感谢！

不谢,以后大家多交流