• 易迪拓培训,专注于微波、射频、天线设计工程师的培养
首页 > 电子设计 > PCB设计 > Mentor PCB设计问答 > dxdesigner 画原理图出错

dxdesigner 画原理图出错

录入:edatop.com     点击:

我用dxdesigner 画原理图,加总线之后出现如下错误。

viewbase: Error 234: Error - The WIR file for CPU.1 has error(s), correct and recheck the schematic:

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D5.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D10.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D15.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D14.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D13.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D12.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D11.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D9.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D8.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D7.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D6.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D4.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D3.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D2.

viewbase: Note 236: - Net and/or Bus has 2 names -- D1 and D0.
我把d1 去掉后,他就说d2有问题。

好奇怪,哪里没有弄对呢?

bu hui de ba!

网络或总线重复命名了,或者总线名和连到他上面的网络的名称不一致。你仔细检查一下你原理图的网络名和总线名,有没有重复或不一致的地方,注意一下你的sym上有没有附加的网络名。

Cadence Allegro 培训套装,视频教学,直观易学

上一篇:软件弹出警告
下一篇:各位有WG2005的老大进来看看

PCB设计培训课程推荐详情>>

  网站地图