- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
请教关于转网络表的疑惑?
录入:edatop.com 点击:
ORCAD----ALLEGRO(PSD15.0)
提示为:
********************************************************************************
*
* Design Rules Check
*
********************************************************************************
Checking Pins and Pin Connections
--------------------------------------------------
Checking Schematic: SCHEMATIC1
--------------------------------------------------
Checking Electrical Rules
Checking for Unconnected Nets
Checking for Invalid References
[DRC0011] Reference is invalid for this part /
Checking for Duplicate References
Check Bus width mismatch
********************************************************************************
*
* Netlisting the design
*
********************************************************************************
Design Name:
f:\vfbs_2.dsn
Netlist Directory:
F:\allegro
Configuration File:
C:\Cadence\PSD_15.0\tools\capture\allegro.cfg
Spawning... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "f:\vfbs_2.dsn" -n "F:\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "CB Footprint"
Scanning netlist files ...
Loading... F:\allegro/pstchip.dat
Loading... F:\allegro/pstchip.dat
Loading... F:\allegro/pstxprt.dat
#38 DDB_ERROR: Terminating character ':' not found on line 11.
DDB_INFO: File F:\allegro/pstxprt.dat not loaded.
Error: Line 11 in file F:\allegro/pstxprt.dat:
Error loading the parts list file
Detected in function: ddbLoadPstXFiles
#1 Error [ALG0036] Unable to read logical netlist data.
Exiting... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "f:\vfbs_2.dsn" -n "F:\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "CB Footprint"
*** Done ***
提示为:
********************************************************************************
*
* Design Rules Check
*
********************************************************************************
Checking Pins and Pin Connections
--------------------------------------------------
Checking Schematic: SCHEMATIC1
--------------------------------------------------
Checking Electrical Rules
Checking for Unconnected Nets
Checking for Invalid References
[DRC0011] Reference is invalid for this part /
Checking for Duplicate References
Check Bus width mismatch
********************************************************************************
*
* Netlisting the design
*
********************************************************************************
Design Name:
f:\vfbs_2.dsn
Netlist Directory:
F:\allegro
Configuration File:
C:\Cadence\PSD_15.0\tools\capture\allegro.cfg
Spawning... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "f:\vfbs_2.dsn" -n "F:\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "CB Footprint"
Scanning netlist files ...
Loading... F:\allegro/pstchip.dat
Loading... F:\allegro/pstchip.dat
Loading... F:\allegro/pstxprt.dat
#38 DDB_ERROR: Terminating character ':' not found on line 11.
DDB_INFO: File F:\allegro/pstxprt.dat not loaded.
Error: Line 11 in file F:\allegro/pstxprt.dat:
Error loading the parts list file
Detected in function: ddbLoadPstXFiles
#1 Error [ALG0036] Unable to read logical netlist data.
Exiting... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "f:\vfbs_2.dsn" -n "F:\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "CB Footprint"
*** Done ***
我也遇到过这样的问题,什么原因不太清楚,我解决的办法是:
重新建立一个project,然后把以前每页的内容copy过来就可以了
Cadence Allegro 培训套装,视频教学,直观易学
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