- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
求Cadence SPB16.2 Hotfix
录入:edatop.com 点击:
TLF有了Cadence SPB16.2 Hotfix。但级别太低,老连不上服务器,下不下来。谁有呢?分享一下?
已上传至Cadence_SPB16.2_by_dzkcool目录下。
20 Dec 2008 SPB16.20.001, Version: SPB:Hotfix:16.20.001~wint
打了补丁后记得要重新用nolic破解一遍。
HOTFIX VERSION: 001
========================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
========================================================================================================
191020 ALLEGRO_EDITOR SHAPE Shape edits results in same net DRC being reported.
230469 ALLEGRO_EDITOR SHAPE Allegro improve performance of Dynamic Shapes
295039 ALLEGRO_EDITOR DFA Allegro DFA to be enhanced to include height
346863 CIS DESIGN_VARIANT Variant View mode is not working for multi-section parts
400036 CONCEPT_HDL HPF nihongo_vector_font should be listed in the Plot Setup GUI
410092 CONCEPT_HDL OTHER The Imported sheets loses the write permission for the group
415462 CONCEPT_HDL MARKERS The SPB157 Markers does not normally display the Japanese fon
501802 ALLEGRO_EDITOR GRAPHICS When hilighting parts or nets the system is inconsistent on z
503526 SPIF OTHER SPIF is NOT defining class for class to class rules.
511175 CONCEPT_HDL CORE Copy All causes - No object selected error
526774 LIBRARY DEVELOPER Pin抯 text size goes back to default size after change pin na
533536 CONCEPT_HDL OTHER The font used in published PDF is not identical.
537769 CONCEPT_HDL CORE Sporadic behavior of DE HDL toolbars for adding components ge
544519 ALLEGRO_EDITOR MENTOR mbs2lib Generating extra "b" version of footprint during tran
551528 LAYOUT OTHER Layout2Allegro L2A translator not translating reference desig
551614 SIG_INTEGRITY IRDROP Import and export of IR-Drop setup
552127 LIBRARY LIBUTIL When -lib is missing from con2con PTF files get re-written in
560417 ALLEGRO_EDITOR OTHER Part Logic does not read part row from ptf file and assign in
564954 CONCEPT_HDL CREFER Crefer attaches $XR property to other $XR on RHEL.
565798 CIS DESIGN_VARIANT all the sections of mult part package are not coming as DNS i
571627 CONCEPT_HDL CONSTRAINT_MGR cmuprev fails to synchronize constraints on low assertion vec
577915 CONCEPT_HDL ARCHIVER zero folder is not archived how the archiver is working ?
581446 LAYOUT TRANSLATION L2A fails with pin numbers do not match between symbols from
583891 ALLEGRO_EDITOR MENTOR Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
586998 ALLEGRO_EDITOR PLOTTING Board shifts towards top left when plotting at higher resolut
587870 ALLEGRO_EDITOR PCAD_IN Import PCAD fails due to dupliate pad name. Caused by a peri
588949 CONCEPT_HDL CORE Importing schematic pages from another project crashes Concep
592340 ALLEGRO_EDITOR MENTOR MBS2LIB not creating the correct shape in symbol
596530 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translator removing/renaming reference design
596638 ALLEGRO_EDITOR EDIT_ETCH The timing meter indicates untruthful violation
596716 PSPICE DEHDL Flag error due to part pin mismatch while create netlist
597685 ALLEGRO_EDITOR SCHEM_FTB ratnest are out of date error in DBDoctor after import logic
597937 ALLEGRO_EDITOR PADS_IN Request PADs_in to translate keepout areas
598575 ALLEGRO_EDITOR OTHER During Split plane should it use settings regarding fill styl
598814 APD WIREBOND bondfinger does not move relative to its origin using ipick
599823 CONCEPT_HDL CONSTRAINT_MGR Lost ref to dml-lib causes loss of cm data even if the refere
599886 APD EXPORT_DATA bodygen batch tool is failing to generate .css file
603425 SPECCTRA PARSER Do file fails Syntax error in command unexpected end-of-line
603987 APD OTHER Offset via generator should ensure pitch distance is met or e
604377 SCM PACKAGER Output board name containing a dash causes scm crash
604614 CONSTRAINT_MGR OTHER netrev is unable to update the Canonical paths with the new d
604794 ALLEGRO_EDITOR PAD_EDITOR Replace Padstack reports error pad missing not true.
605169 ALLEGRO_EDITOR OTHER Can design_compare handle swappable pins?
606586 ALLEGRO_EDITOR INTERFACES Multiple drill in padstack cannot be shown in Pro/E IDF
607217 APD IO_PLANNER wirebond die replacement from IOP
607222 APD WIREBOND auto wirebonding creates wirebond with DRC
607644 ALLEGRO_EDITOR MANUFACT Enhancement to increase the IDF export ''default package heig
607718 CONCEPT_HDL HDLDIRECT HDL Direct Errors reported while generating simulation netlis
608233 SIG_INTEGRITY FIELD_SOLVERS Convergence errors with analytical vias when drill size is 1
609549 ALLEGRO_EDITOR INTERACTIV Mirror Geometry command to change BB Via's layer.
610028 SIP_LAYOUT IMPORT_DATA De assign NC nets during aif import
610134 CONSTRAINT_MGR INTERACTIV Cross-probing from CM to Allegro no longer works on system le
610276 ALLEGRO_EDITOR PADS_IN PADS to Allegro translation is failing with error.
610482 ALLEGRO_EDITOR SCHEM_FTB Netlist swapped net names on 2 pins causing shape to lose its
610681 CONSTRAINT_MGR DATABASE An exported constraint file can not be re-imported in V16.01
611260 ALLEGRO_EDITOR DRC_CONSTR Routing a diff pair it does not follow Physical line width se
611425 ALLEGRO_EDITOR MENTOR mbs2brd crashes when importing Mentor
611697 SIP_FLOW SIP_LAYOUT octagonal bumps have offset in SIP compared to the chip view
611807 APD WIREBOND Duplicate paths created on wirebond import for some cases.
611856 CONCEPT_HDL GLOBALCHANGE Ref des deletions after runnning Global Change to change $LOC
611874 CONCEPT_HDL OTHER Crossprobing one symbol in Concept using Occurence edit mode
612088 PSPICE DEHDL_NETLISTER Fail to create the netlist for G value expression
612195 ALLEGRO_EDITOR DATABASE Adding layers to the default cross section causes phantom tex
612237 ALLEGRO_EDITOR SKILL axlFormColorize does not change the full background area of a
612299 APD DEGASSING Degassing static shape creates voids inside of voided areas
612560 CONSTRAINT_MGR OTHER Diffpairs don't show the CSet assigned through Net Class
612587 APD WIREBOND Unchecked Allow DRC option creating disconnected wire bond.
612884 SIG_INTEGRITY SIMULATION When using ViaModel
612914 ALLEGRO_EDITOR EDIT_ETCH Centered via option in fanout command not available when swit
612939 SIP_LAYOUT ASSY_RULE_CHECK ADRC Continuous Solder Mask check problem
613553 CONCEPT_HDL EDIF300 edif schematic writer crash on this design
613565 ALLEGRO_EDITOR EDIT_ETCH Allegro Editor Differential Pairs are routing incorrectly
613736 SPIF OTHER Spif fails to write class data
613990 POWER_INTEGRIT INTERACTIV PI is crashing during capacitor selection
614278 CONCEPT_HDL EDIF300 pin text note and flag are not visible on reloaded edif file
614371 SIP_LAYOUT WIREBOND Any wirebond command crashes the application
614407 POWER_INTEGRIT INTERACTIV PI crashes when editing capacitors
614727 SPECCTRA GUI Allegro PCB Router can not process the dsn and rules file for
614972 ALLEGRO_EDITOR SKILL axlCNSSetSpacing does not change the value of the "testvia to
615144 SIP_LAYOUT 3D_VIEWER die placement does not change with changing in soldermask thi
615431 LAYOUT TRANSLATORS padstack names are crippled or renamed if it has over 18 Char
615506 APD MANUFACTURING Sort by die pin location for Manufacture Doc Bond finger brok
615745 SIP_LAYOUT DATABASE Move die symbol with stretch etch on is disconnecting wires f
615816 SPIF OTHER Allegro match group members not translating to PCB Router; mi
616104 CONSTRAINT_MGR OTHER allegroTechnologyFile XML format issue
616122 LAYOUT TRANSLATORS Protel to MAX translator problem with package outlines and re
616404 ALLEGRO_EDITOR OTHER Design compare fails with message "Invalid input argument" wh
616713 CIS PLACE_DATABASE_PAR property name with "&" charecter in access database causing c
616818 SCM PACKAGER BOMHDL -type scm fails on schematic block
616907 SCM VERILOG_IMPORT scm crash during Get Module Name
617058 APD WIREBOND wirebond space evenly does not work for fingers on power ring
617083 ALLEGRO_EDITOR INTERACTIV Windows tabs hangs on Linux
617236 ALLEGRO_EDITOR SHAPE Editing a shape in a void causes the bigger shape to drop seg
617351 CIS DBC_CFG_WIZARD XML writer fails if DBC location doesnt have write permission
617515 SIP_LAYOUT OTHER Be able to invoke Velocity from cdnsip
617761 LAYOUT TRANSLATORS Value property for Library symbol of Orcad Layout is not tran
617890 SIP_LAYOUT WIREBOND Push and shove on Bond fingers with multiple bond wires cause
618184 APD OTHER database diary on unix/linux
618201 ALLEGRO_EDITOR OTHER Dynamic fillets take a long time to complete
618545 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we place a package symbol for Jumper usi
618610 ALLEGRO_EDITOR MANUFACT Delete a cline seg creates a fillet
618651 SIP_LAYOUT IO_PLANNER Bondfingers and die are shifted every time an update package
618712 ALLEGRO_EDITOR EDIT_ETCH Shove mode is not working on Diff pairs in PCB Design L
618836 ALLEGRO_EDITOR SCRIPTS Allegro does not interpret recorded macro script files proper
618946 ALLEGRO_EDITOR INTERACTIV Allegro crashes while using Place Manual -H
618984 ALLEGRO_EDITOR COLOR Layers on Allegro Canvas does not match Color Dialog Box
619007 ALLEGRO_EDITOR SKILL Skill command does not accept spaces in file path/name
619033 F2B PACKAGERXL Pinswap lost on backannotation
619268 POWER_INTEGRIT SIMULATION IR-Drop can't sees via on pad as open
619356 CIS FOOTPRINT_VIEW Footprint preview only from 1 directory in Capture.INI
619712 ALLEGRO_EDITOR EDIT_ETCH Unable to route in the Bubble Mode for Partitioned board
619773 ALLEGRO_EDITOR DATABASE Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
620064 CONCEPT_HDL CONSTRAINT_MGR Loosing Diff pair constraints from lower blocks when packagin
622132 CAPTURE NETLIST_ALLEGRO Incorrect ALG0078 error for complex hierarchical design
TLF是什么哦,是不是指在FTP上啊!
www.eastgame.net
下到了SPB16.2 Hotfix的人路过
看来也下不了,还没有注册呢!
TOUHOU你下到了,共享下啊!
不知道HOTRIX补了些什么
软件还没出来几天,补丁就下来了?、、
分流
Hotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)
谢谢啦!下来看看
开了2天电脑,就下了30多k,谁能提供下载呢?
看下面链接,你就知道了,里面的资源太多了:
http://www3.eastgame.net/index.php
我看到至少有三个人完成下载了,emule下载需要耐心.
下载了的可以用qq或者是邮箱传一下的嘛!速度很快的,今天误删了license server 重新安装上去就不能用了
这三个人中有一个是我,改天帮助大家加速
我就是在tlf的S15服务器下的。
DDD