• 易迪拓培训,专注于微波、射频、天线设计工程师的培养
首页 > 电子设计 > PCB设计 > Allegro PCB技术问答 > 请教:oracd DRC检查没有错误但不能生成网表!

请教:oracd DRC检查没有错误但不能生成网表!

录入:edatop.com     点击:
各位大佬:
我是新手,我用orcad画完原理图,drc检查没有错误,但就是不能生成网表,请教:谢谢!
log:

Loading... C:\Documents and Settings\Administrator.ASUSTEK-4295C4C\桌面\sch\allegro/pstchip.dat
#72 ERROR(SPCODD-72): A mismatch in the number of sections occurred on line 1701 while parsing logical pins.
        To avoid such errors, use Part Developer instead of manually editing the library part definition
              ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.
#21 Error   [ALG0036] Unable to read logical netlist data.

中文路径

我改成全英文路径也是提示错误,一样de错误log,呜,

Cadence Allegro 培训套装,视频教学,直观易学

上一篇:allegro PCB Editor 15.2的问题
下一篇:有了原理图,如何将它转换成net

PCB设计培训课程推荐详情>>

  网站地图