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新使用发现的出错提示

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------ Preparing to read pst files ------
Starting to read F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstchip.dat
   Finished reading F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstchip.dat (00:00:00.00)
Starting to read F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstxprt.dat
   Finished reading F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstxprt.dat (00:00:00.01)
Starting to read F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstxnet.dat
   Finished reading F:/ZSGWORK/DESIGN-PCB/spfx_g_1v2/allegro/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------
#1   ERROR(302) Device library error detected.
Problems with device 'RESISTOR_SM/R_0805'. JEDEC_TYPE property 'SM/R_0805' is illegal: 'Package name has invalid characters or is too long.'.
Device 'RESISTOR_SM/R_0805' has library errors. Unable to transfer to Allegro.
------ Summary Statistics ------
#2   ERROR(102) Run stopped because errors were detected
netrev run on May 24 13:31:34 2010
   DESIGN NAME : 'SPFX_G1V3'
   PACKAGING ON May  5 2005 19:14:45
   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON
  2 errors detected
No oversight detected
No warning detected
cpu time      0:00:17
elapsed time  0:00:01
那位高手能看懂不?
pcb封装名长了不可以嘛?图纸可是前任留下的--他如何使用时可以呢--不懂呢

SM/R_0805有问题啊,不能用/

封装命名中不能有"/"

封装命名含有非法字符,PCB库中的封装名称中的特殊符号只能用半角状态下划线”_”

谢谢了---我是拿来就用的--刚上手

Cadence Allegro 培训套装,视频教学,直观易学

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