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allegro pcb 导入网表
录入:edatop.com 点击:
在orcad中对原理图进行drc和网表设置后,再进行pcb导入网表时,报错为:(简单原理图和复杂的原理图都是一样的报错结果)
Cadence Design Systems, Inc. netrev 16.2 Fri Apr 23 10:17:58 2010
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'D:/CadenceProject/1';
BOARD_DIRECTORY '';
OLD_BOARD_NAME '1222.brd';
NEW_BOARD_NAME '1222.brd';
CmdLine: netrev -$ -i D:/CadenceProject/1 -y 1 D:/CadenceProject/1/#Taaaaaa00840.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Apr 23 10:17:58 2010
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:23
elapsed time 0:00:00
我是新手,不知道是哪一步设置错误,请各位大虾帮忙!
Cadence Design Systems, Inc. netrev 16.2 Fri Apr 23 10:17:58 2010
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'D:/CadenceProject/1';
BOARD_DIRECTORY '';
OLD_BOARD_NAME '1222.brd';
NEW_BOARD_NAME '1222.brd';
CmdLine: netrev -$ -i D:/CadenceProject/1 -y 1 D:/CadenceProject/1/#Taaaaaa00840.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Apr 23 10:17:58 2010
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:23
elapsed time 0:00:00
我是新手,不知道是哪一步设置错误,请各位大虾帮忙!
封装没找到,你做的封装路径要设置好,包括用到的封装和封装的焊盘路径
谢谢!我用的是allegro中指定的封装路径。并在setup——user preferences editor。加载了,默认的封装。可是还是错位!
你的PCB editor以前成功生成过PCB板吗?如果以前生成过说明不是软件的问题,我不知道你用的是哪个版本,我用的是16.3的,然后在设置路径时要设置两个,padpath和psmpath,你这两个都设了吗?还有就是你去软件自带的封装库和你自己定义的封装库看一下,确定一下设置的路径没有问题
一直就没成功生成过。不管是简单的还是复杂的。所报告的错误大概都是这个意思!
我用的是16.2的,所设置的路径和你的一样。悲哀!
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