首页 > 电子设计 > PCB设计 > Allegro PCB技术问答 > 原理图检查没错，也可以生成网表。但是导入网表的时候出现以下错误！

原理图检查没错，也可以生成网表。但是导入网表的时候出现以下错误！

录入：edatop.com 点击：

(---------------------------------------------------------------------)
(                                                                   )
( Netrev Allegro Import Logic                                     )
(                                                                   )
( Drawing       : tmt.brd                                     )
( Software Version : 16.3p004                                     )
( Date/Time       : Sun Aug 08 12:12:28 2010                   )
(                                                                   )
(---------------------------------------------------------------------)

------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'F:/fuzhitmt';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'F:/fuzhitmt/allegro/tmt.brd';
NEW_BOARD_NAME 'F:/fuzhitmt/allegro/tmt.brd';
CmdLine: netrev -$ -i F:/fuzhitmt -y 1 F:/fuzhitmt/allegro/#Taaaaaa03408.tmp
------ Preparing to read pst files ------
Starting to read F:/fuzhitmt/pstchip.dat
Finished reading F:/fuzhitmt/pstchip.dat (00:00:00.21)
Starting to read F:/fuzhitmt/pstxprt.dat
Finished reading F:/fuzhitmt/pstxprt.dat (00:00:00.00)
Starting to read F:/fuzhitmt/pstxnet.dat
Finished reading F:/fuzhitmt/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------

#1 ERROR(SPMHNI-191): Device/Symbol check error detected.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '6'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '5'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '7'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '9'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '10'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '8'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '13'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '12'.
ERROR(SPMHNI-195): Symbol 'SOT23-3' for device '2N6988_SOT23-3_2N6988' is missing pin '14'.
------ Library Paths ------
MODULEPATH =  .
         D:/Cadence/SPB_16.3/share/local/pcb/modules
PSMPATH =  .
         symbols
         ..
         ../symbols
         D:/Cadence/SPB_16.3/share/local/pcb/symbols
         D:/Cadence/SPB_16.3/share/pcb/pcb_lib/symbols
         D:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols
         F:\fengzhuangxinxi\TMT\
         F:\fengzhuangxinxi\TML\
PADPATH =  .
         symbols
         ..
         ../symbols
         D:/Cadence/SPB_16.3/share/local/pcb/padstacks
         D:/Cadence/SPB_16.3/share/pcb/pcb_lib/symbols
         D:/Cadence/SPB_16.3/share/pcb/allegrolib/symbols
         F:\fengzhuangxinxi\TMT\
         F:\fengzhuangxinxi\TML\

------ Summary Statistics ------

#2 Run stopped because errors were detected
netrev run on Aug 8 12:12:28 2010
DESIGN NAME : 'TMT'
PACKAGING ON Nov 17 2009 03:09:43
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
  2 errors detected
No oversight detected
No warning detected
cpu time    0:02:36
elapsed time  0:00:02

好心人帮忙解决一下

SOT23-3封装的器件，原理图sym和footprint的pin脚定义不一致

封装的问题
我也遇到过

建议重新做封装肯定没问题

原理图与PCB封装不一致。
如果封装库不是自己在弄的，这种问题很常见。

谢谢

我试试啊，谢谢了

我确实用的不是自己的封装库，唉~~~

0.0

哈哈，常見的問題。

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原理图检查没错，也可以生成网表。但是导入网表的时候出现以下错误！

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