求助，此PADS转入ALLEGRO走线一根都没有了

Translating E:\WORK\TEST\1.asc.
Reading PADS ASCII file header.
Version = PowerPCB5.0
Route Layers = 4
Units = METRIC
Hatch mode = Vertical / Horizontal
Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 0.000315
Initializing new database.
Creating layers.
Reading PADS ASCII file body.
*PARTTYPE*
*MISC*
*MISC*
*MISC*
*MISC*
*MISC*
*REUSE*
*TEXT*
*LINES*
*VIA*
*PARTDECAL*
*PARTTYPE*
*PART*
*ROUTE*
Writing routes.
*END*
===============================================================================
PADS layer usage summary:
  Layers 1 to 4 are route layers.
  LINES:
     0 BOARD GEOMETRY - ALL
     1           ETCH - TOP
     3           ETCH - INTERNAL2
     4           ETCH - BOTTOM
     9  * Not mapped！
    10  * Not mapped！
  COPPER:
  TEXT:
     1           ETCH - TOP
    26  * Not mapped！
  DECALS:
     0 PACKAGE GEOMETRY - SILKSCREEN_TOP
     1 PACKAGE GEOMETRY - SILKSCREEN_TOP
    12  * Not mapped！
    19  * Not mapped！
    26  * Not mapped！
  PADS:
     0           ETCH - internal_pad_def
     1           ETCH - TOP
     2           ETCH - INTERNAL1
     3           ETCH - INTERNAL2
     4           ETCH - BOTTOM
     6  * Not mapped！
    15  * Not mapped！
    16  * Not mapped！
    23  * Not mapped！
  VIAS:
     0      VIA CLASS - internal_pad_def
     1      VIA CLASS - TOP
     2      VIA CLASS - INTERNAL1
     3      VIA CLASS - INTERNAL2
     4      VIA CLASS - BOTTOM
WARNING: 63 data objects mapped to the UNUSED class were ignored.
===============================================================================
Creating E:\WORK\TEST\1.brd.
Loading netlist:
E:\WORK\TEST\1.TXT
Writing database.
ERROR: Error while writing the Allegro database.
Closing database.
Translation complete.
Finished with errors！

这个问题说明你的在导出的时候选择有些问题，在导出的时候这是非常关键的一步骤！

兄弟别的板子我随便都导成功，只有这个板怪得很

这个接口做得一般，，
所以有问题很正常