- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
请问这个是因为什么导入不了网表,加急!
录入:edatop.com 点击:
netrev run on Oct 29 15:11:18 2012
DESIGN NAME : '522'
PACKAGING ON Apr 11 2011 13:01:17
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
No error detected
No oversight detected
1 warnings detected
cpu time 0:00:48
elapsed time 0:00:00
DESIGN NAME : '522'
PACKAGING ON Apr 11 2011 13:01:17
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
No error detected
No oversight detected
1 warnings detected
cpu time 0:00:48
elapsed time 0:00:00
提示没有错误啊,怎么会导不进,很有可能是你的库文件的路径没有设置正确,你再好好检查一下路径吧!
Cadence Allegro 培训套装,视频教学,直观易学
上一篇:shape变成LINE属性
下一篇:关于DDR时钟的Xnet的差分对设置问题讨论