- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
allegro 导入网表出错
IPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'E:/学习资料/cadence_practice/my_schematic';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/学习资料/cadence_practice/my_pcb/dsp6713.brd';
NEW_BOARD_NAME 'E:/学习资料/cadence_practice/my_pcb/dsp6713.brd';
CmdLine: netrev -$ -i E:/学习资料/cadence_practice/my_schematic -y 1 E:/学习资料/cadence_practice/my_pcb/#Taaaaaa03712.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jan 20 15:58:54 2013
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:31
elapsed time 0:00:00
有中文字符.
谢谢,不过这下我改成英文了,好像还是不行,求解······
(---------------------------------------------------------------------)
( )
( Allegro Netrev Import Logic )
( )
( Drawing : dsp6713.brd )
( Software Version : 16.5P002 )
( Date/Time : Sun Jan 20 17:36:09 2013 )
( )
(---------------------------------------------------------------------)
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'E:/learning/cadence_practice/my_schematic';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'E:/learning/cadence_practice/my_pcb/dsp6713.brd';
NEW_BOARD_NAME 'E:/learning/cadence_practice/my_pcb/dsp6713.brd';
CmdLine: netrev -$ -i E:/learning/cadence_practice/my_schematic -y 1 E:/learning/cadence_practice/my_pcb/#Taaaaaa02008.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jan 20 17:36:09 2013
刷个屏,请大神帮忙瞅瞅啊······
网表应该没导出来,allegro找不到相关的文件
创建网表时好像没提示错误啊,建立allegro文件夹里面的东西如图中所示,不晓得是不是有了,第一次玩这个,麻烦瞅瞅啊,谢谢
网表路径不对,导入时检查下是不是你导出网表的那个文件夹。
网表路径不对,你的网表出在allegro文件夹下面,但是导网表的路径却设置在上一级,即my schematic下面
谢谢,导进来了
谢谢,导进来了,呵呵
终于看懂一个。
Cadence Allegro 培训套装,视频教学,直观易学
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