- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
请教各位高手导入网表的问题
录入:edatop.com 点击:
小弟最近做了一块板,导入网表时出错,请各位高手提供些建议!谢了!
(---------------------------------------------------------------------)
( )
( Netrev Allegro Import Logic )
( )
( Drawing : DUDEMO.brd )
( Software Version : 16.3p004 )
( Date/Time : Sun Jun 09 19:07:58 2013 )
( )
(---------------------------------------------------------------------)
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'D:/mypcblib/mypojc';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:/mypcblib/mypojc/DUDEMO.brd';
NEW_BOARD_NAME 'D:/mypcblib/mypojc/DUDEMO.brd';
CmdLine: netrev -$ -i D:/mypcblib/mypojc -y 1 D:/mypcblib/mypojc/#Taaaaaa15232.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jun 9 19:07:58 2013
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:58
elapsed time 0:00:00
(---------------------------------------------------------------------)
( )
( Netrev Allegro Import Logic )
( )
( Drawing : DUDEMO.brd )
( Software Version : 16.3p004 )
( Date/Time : Sun Jun 09 19:07:58 2013 )
( )
(---------------------------------------------------------------------)
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'D:/mypcblib/mypojc';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'D:/mypcblib/mypojc/DUDEMO.brd';
NEW_BOARD_NAME 'D:/mypcblib/mypojc/DUDEMO.brd';
CmdLine: netrev -$ -i D:/mypcblib/mypojc -y 1 D:/mypcblib/mypojc/#Taaaaaa15232.tmp
------ Preparing to read pst files ------
#1 ERROR(24) File not found
Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jun 9 19:07:58 2013
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
2 errors detected
No oversight detected
No warning detected
cpu time 0:00:58
elapsed time 0:00:00
没有指定封装库路径
#1 ERROR(24) File not found
倀愀挀欀愀最攀爀 files not found
应该是网表所在的路径都没有读对吧。
有三个问题,一个是文件路径不对,第二个少一个封装文件!第三个封装做的不对!已解决,谢谢你的回复
楼上怎么解决的,我刚开始用orcad 导网络表同样遇到和小编一样的问题,麻烦指点下,谢谢
Cadence Allegro 培训套装,视频教学,直观易学
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