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关于allegro 的database check的相关问题讨论
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大家好，同样一块板子，第一次artwork时没有问题，第二次增加了两侧的工艺边后，artwork是报错，Dbcheck不通过，然后进行database check 一下为database的描述：
********************************************************************************
* Performance checking for design Z:/E/supcon/PRD-13002/hardware/ESP-300 V1.1/ESP-300 V1_1.brd
********************************************************************************
Ratsnest schedule check
-------------------------------
* OK.
DRC check
----------------------
* The number of physical/spacing csets is 0.060241 larger than the number
of nets Suggest examining constraint model.
ISSUE: Misuse of the Allegro constraint model such as using a spacing
cset for each diffpair in the design. Result is system
performance degradation.
Constraint region check
-------------------------------
* Region on all - MINIUSB: Suggest use by layer or outer/inner regions.
ISSUE: Encourage use of new layer based regions which helps performance and
simplifies constraint management.
shape/region location: (35.1028,-31.5976)
class: CONSTRAINT REGION subclass: ALL
* Region on all - CPU: Suggest use by layer or outer/inner regions.
ISSUE: Encourage use of new layer based regions which helps performance and
simplifies constraint management.
shape/region location: (7.9883,19.2659)
class: CONSTRAINT REGION subclass: ALL
Dynamic shape check
-------------------------------
* OK.
Sector table check
-------------------------------
* The ratio of design extent to route keepin extent is too large (10.375068). Suggest reducing design extent.
Constraint set check
---------------------------------
* Unused csets list (4):
ISSUE: Design maintenance issue, slight performance impact.
SNCS: SN-POW
PCS: PHY-LCDBG
PCS: PHY-POW
SCS: SCSET-POW
NODRC_SYM_SAME_PIN check
---------------------------------
* OK.
Cross section check for bad dielectric constant values
--------------------------------------------------------
* OK.
Padstack size check
---------------------------------
* OK.
4 problems found. 1 maintenance problems found.
问题：
1、artwork时是否有勾选实时数据检查；
2、database check中哪些可以忽略，甚至屏蔽；
还有相关问题可提出，望大家一起，群策群力！
********************************************************************************
* Performance checking for design Z:/E/supcon/PRD-13002/hardware/ESP-300 V1.1/ESP-300 V1_1.brd
********************************************************************************
Ratsnest schedule check
-------------------------------
* OK.
DRC check
----------------------
* The number of physical/spacing csets is 0.060241 larger than the number
of nets Suggest examining constraint model.
ISSUE: Misuse of the Allegro constraint model such as using a spacing
cset for each diffpair in the design. Result is system
performance degradation.
Constraint region check
-------------------------------
* Region on all - MINIUSB: Suggest use by layer or outer/inner regions.
ISSUE: Encourage use of new layer based regions which helps performance and
simplifies constraint management.
shape/region location: (35.1028,-31.5976)
class: CONSTRAINT REGION subclass: ALL
* Region on all - CPU: Suggest use by layer or outer/inner regions.
ISSUE: Encourage use of new layer based regions which helps performance and
simplifies constraint management.
shape/region location: (7.9883,19.2659)
class: CONSTRAINT REGION subclass: ALL
Dynamic shape check
-------------------------------
* OK.
Sector table check
-------------------------------
* The ratio of design extent to route keepin extent is too large (10.375068). Suggest reducing design extent.
Constraint set check
---------------------------------
* Unused csets list (4):
ISSUE: Design maintenance issue, slight performance impact.
SNCS: SN-POW
PCS: PHY-LCDBG
PCS: PHY-POW
SCS: SCSET-POW
NODRC_SYM_SAME_PIN check
---------------------------------
* OK.
Cross section check for bad dielectric constant values
--------------------------------------------------------
* OK.
Padstack size check
---------------------------------
* OK.
4 problems found. 1 maintenance problems found.
问题：
1、artwork时是否有勾选实时数据检查；
2、database check中哪些可以忽略，甚至屏蔽；
还有相关问题可提出，望大家一起，群策群力！
