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cadence导入网络表出错

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(---------------------------------------------------------------------)
(                                                                   )
( Allegro Netrev Import Logic                                     )
(                                                                   )
( Drawing       : s301pcb_dianchi.brd                         )
( Software Version : 16.5P002                                     )
( Date/Time       : Wed Jul 03 11:06:07 2013                   )
(                                                                   )
(---------------------------------------------------------------------)

------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_DELETE_FIRST_SEGMENT FALSE;
RIPUP_RETAIN_BONDWIRE FALSE;
RIPUP_SYMBOLS ALWAYS;
Missing symbol has error FALSE;
SCHEMATIC_DIRECTORY 'C:/SPB_Data/BRDword';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'C:/SPB_Data/BRDword/s301pcb_dianchi.brd';
NEW_BOARD_NAME 'C:/SPB_Data/BRDword/s301pcb_dianchi.brd';
CmdLine: netrev -$ -i C:/SPB_Data/BRDword -y 1 C:/SPB_Data/BRDword/#Taaaaaa04396.tmp
------ Preparing to read pst files ------

#1 ERROR(24) File not found
   Packager files not found
#2 ERROR(102) Run stopped because errors were detected
netrev run on Jul 3 11:06:07 2013
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
  2 errors detected
No oversight detected
No warning detected
cpu time    0:00:25
elapsed time  0:00:00

#1 ERROR(24) File not found
Packager files not found

封装库的路径没有设置吧?

哦，谢谢，我试试

已经调整过了，是PCB library与元理图命名不一样

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