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Cadence SPB OrCAD 16.50.46
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Cadence SPB OrCAD 16 最新的升级补丁，版本号16.50.46，修正内容如下：
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================
1079538 F2B PACKAGERXL Ability to block all їsingle noded netsї to the board while packaging.
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.
1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.
1160004 SCM UI The RMB->Paste does not insert signal names.
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
1165469 CONCEPT_HDL CORE Import Design loses design library name
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
Cadence SPB OrCAD 16.50.46 Hotfix
Download uploaded
http://uploaded.net/file/9yjz448a/cpborc165046ho.rar
Download 城通网盘
http://www.400gb.com/file/28712279
CCRID PRODUCT PRODUCTLEVEL2 TITLE
===================================================================================
1079538 F2B PACKAGERXL Ability to block all їsingle noded netsї to the board while packaging.
1123150 CONCEPT_HDL CORE property on y axis in symbol view was moved by visibility change to None.
1144990 PCB_LIBRARIAN CORE PDV expand & collapse vector pins resizes symbol outline to maximum height
1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushing the part name suffix into vendor_part_number value
1152755 CONCEPT_HDL COPY_PROJECT Copy project hangs if library or design name has an underscore
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
1155569 APD MODULES P1_U1 and P1_U3 Die pins are missing after Place Module.
1155728 CONCEPT_HDL CORE Unable to uprev packaged 16.3 design in 16.5 due to memory
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule check through pin Etch makes confused.
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file name in uppercase.
1158528 CONCEPT_HDL OTHER Dual Monitor issue: Retain Hard Packaging option is missing and attribute test distorted
1158718 CONCEPT_HDL CHECKPLUS Customer could not get $PN property values on logical rule of CheckPlus16.6.
1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with new slide.
1160004 SCM UI The RMB->Paste does not insert signal names.
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
1165469 CONCEPT_HDL CORE Import Design loses design library name
1165801 CONCEPT_HDL PDF Pin texts of spun symbol overlap in publish PDF.
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
1167519 ALLEGRO_EDITOR DATABASE Uprev dbdoctor does not log warnings about renaming properties.
Cadence SPB OrCAD 16.50.46 Hotfix
Download uploaded
http://uploaded.net/file/9yjz448a/cpborc165046ho.rar
Download 城通网盘
http://www.400gb.com/file/28712279
谢谢搂主,下载了.
谢谢分享啊，辛苦了
谢谢小编
