- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
原理图不能生成网表问题
录入：edatop.com 点击：
Loading... e:\1-4valve\allegro/pstchip.dat
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CA3039/TO_1_3215_M7'. Each section must have at least one non-common pin.
Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
ERROR(SPCODD-47): Packaging can not complete because the file ./allegro/pstchip.dat could not be loaded. There might be syntax errors in this file. Ensure that the syntax is correct before proceeding.
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a nu
ll object ID. The design may not have been saved correctly. Save the design before packaging.
#4 ERROR(ORCAP-36026): Unable to read logical netlist data.
求解决
#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CA3039/TO_1_3215_M7'. Each section must have at least one non-common pin.
Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
ERROR(SPCODD-47): Packaging can not complete because the file ./allegro/pstchip.dat could not be loaded. There might be syntax errors in this file. Ensure that the syntax is correct before proceeding.
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a nu
ll object ID. The design may not have been saved correctly. Save the design before packaging.
#4 ERROR(ORCAP-36026): Unable to read logical netlist data.
求解决
Cadence Allegro 培训套装，视频教学，直观易学
上一篇：叠层设置中一个选项的含义。
下一篇：参考平面层的问题
