• 易迪拓培训,专注于微波、射频、天线设计工程师的培养
首页 > 电子设计 > PCB设计 > Allegro PCB技术问答 > 16.6又出23号补丁了,求下载链接。

16.6又出23号补丁了,求下载链接。

录入:edatop.com     点击:
16.6又出23号补丁了,求下载链接,话说这个更新速度比我的下载速度都快

http://dl.vmall.com/c0fu1auqa8

DATE: 02-14-2014   HOTFIX VERSION: 023
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1120183 F2B            DESIGNVARI       Variant Editor Filter returns incorrect results.
1202715 SPIF           OTHER            Objects loose module group attribute after Specctra
1203443 ADW            LRM              LRM takes a long time to launch for the first time
1207204 CONCEPT_HDL    CORE             schematic tool crashed during save all
1222101 CONCEPT_HDL    CORE             Pins are shorted on a block by the Block's title delimiter
1223709 FSP            FPGA_SUPPORT     Need FSP model of Altera 5AGZME3E3H29C4 FPGA
1224025 ALLEGRO_EDITOR INTERFACES       The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
1225591 F2B            PACKAGERXL       Aliased net signals starting with equals sign are not resolved correctly in cmgr
1226480 ALLEGRO_EDITOR EDIT_ETCH        Routing time is took to double increase when using the Add Connect because DRC is Allowed.
1229234 FLOWS          PROJMGR          Can't open the part table file from Project Setup
1229555 ALLEGRO_EDITOR ARTWORK          IPC-2581 not recognizing pin offsets correctly.
1229610 FSP            FPGA_SUPPORT     New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
1232601 ALLEGRO_EDITOR MANUFACT         Cannot add test point to via on trace.
1232772 ALLEGRO_EDITOR DATABASE         When applying a place replicate module Allegro crashes
1233216 SIP_LAYOUT     DIE_ABSTRACT_IF  Allow more than 2 decimal places for the shrink facor in the add codesign form
1233690 PDN_ANALYSIS   PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
1233977 ALLEGRO_EDITOR INTERFACES       single shape copied and rotated fails to create when importing IDX
1234357 SIP_LAYOUT     SCHEMATIC_FTB    DSMAIN-335: Dia file(s) error has occurred.
1234450 ALLEGRO_EDITOR INTERFACES       clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
1235587 PSPICE         MODELEDITOR      PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
1236571 ALLEGRO_EDITOR GRAPHICS         Allegro display lock up and panning issues
1237415 ALLEGRO_EDITOR INTERFACES       Multidrill pad is exported with single Drill in the STEP File
1237807 ALLEGRO_EDITOR SCHEM_FTB        The line feed code of netview.dat

还是等到第30个再打吧.

谢谢分享!

好快的更新速度

太快了,是好事情还是坏事情呢?

谢谢分享,有人能转存到百度网盘吗?

才刚刚下了22,这不到一个礼拜又出新了,神速啊
谢谢ning

这么快的更新不是什么好事情。

http://pan.baidu.com/s/1eQl7md8

1229664 ALLEGRO_EDITOR SHAPE            Shape not voiding different net pins causing shorts with no DRC's
看到这一条,必须更新啊。

我觉得下载速度跟不上更新速度

谢谢ls!

更新太快了,坐等hotfix30

频繁更新太累了。

Cadence Allegro 培训套装,视频教学,直观易学

上一篇:来请教大神了
下一篇:关于动态铜皮和静态铜皮出光绘区别?

PCB设计培训课程推荐详情>>

  网站地图