- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
allegro k/p 报错
录入：edatop.com 点击：
LISTING: 1 element(s)
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: BOTTOM
Origin xy: (2867.500 3390.000)
Constraint: SMD Pin to Route Keepout Spacing
Constraint Set: DEFAULT
Constraint Type: NET SPACING CONSTRAINTS
Constraint value: 0 MIL
Actual value: 0 MIL
- - - - - - - - - - - - - - - - - - - -
Element type: SHAPE
Class: ROUTE KEEPOUT
Subclass: BOTTOM
- - - - - - - - - - - - - - - - - - - -
Element type: SYMBOL PIN
Class: PIN
PIN: FID3.1
pinuse: UNSPEC
location-xy: (2850.000 3390.000)
element is on a dummy net
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怎么解决啊
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: BOTTOM
Origin xy: (2867.500 3390.000)
Constraint: SMD Pin to Route Keepout Spacing
Constraint Set: DEFAULT
Constraint Type: NET SPACING CONSTRAINTS
Constraint value: 0 MIL
Actual value: 0 MIL
- - - - - - - - - - - - - - - - - - - -
Element type: SHAPE
Class: ROUTE KEEPOUT
Subclass: BOTTOM
- - - - - - - - - - - - - - - - - - - -
Element type: SYMBOL PIN
Class: PIN
PIN: FID3.1
pinuse: UNSPEC
location-xy: (2850.000 3390.000)
element is on a dummy net
- - - - - - - - - - - - - - - - - - - -
怎么解决啊
在 CM 里面根本找不到这一项
自己仔细琢磨琢磨啊
找到答案了
稍微翻译一下，都很好理解
PIN与KEEP OUT干涉了，移开就好
