- 易迪拓培训,专注于微波、射频、天线设计工程师的培养
allegro16.6如何走T型线？
录入：edatop.com 点击：
一个DDR时钟差分线设置为T型走线，但是连上线后，出现DRC错误。
请教一下，是哪里出错了呢，正确的走线方式又是怎么样的呢?
错误如下：
LISTING: 1 element(s)
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: ALL
Origin xy: (-772.35 1153.00)
Constraint: Net Schedule Topology
Constraint Set: ECS2
Constraint Type: NET ELECTRICAL CONSTRAINTS
Constraint value: VERIFY
Actual value: DOES NOT VERIFY
- - - - - - - - - - - - - - - - - - - -
Element type: SYMBOL PIN
Class: PIN
PIN: C254.1
pinuse: UNSPEC
location-xy: (-772.35 1153.00)
part of net name: DSCK#
- - - - - - - - - - - - - - - - - - - -
Element type: RATSNEST TPOINT
Class: DRC ERROR CLASS
Subclass: TOP
Name: DSCK#.T.1
(-745.00 970.00)
- - - - - - - - - - - - - - - - - - - -
请教一下，是哪里出错了呢，正确的走线方式又是怎么样的呢?
错误如下：
LISTING: 1 element(s)
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: ALL
Origin xy: (-772.35 1153.00)
Constraint: Net Schedule Topology
Constraint Set: ECS2
Constraint Type: NET ELECTRICAL CONSTRAINTS
Constraint value: VERIFY
Actual value: DOES NOT VERIFY
- - - - - - - - - - - - - - - - - - - -
Element type: SYMBOL PIN
Class: PIN
PIN: C254.1
pinuse: UNSPEC
location-xy: (-772.35 1153.00)
part of net name: DSCK#
- - - - - - - - - - - - - - - - - - - -
Element type: RATSNEST TPOINT
Class: DRC ERROR CLASS
Subclass: TOP
Name: DSCK#.T.1
(-745.00 970.00)
- - - - - - - - - - - - - - - - - - - -
走线拓扑不对，也就是走线的连接顺序与约束规则设置的不一致。正确的走线顺序要看你板上的约束是怎么设置的。
http://www.eda365.com/thread-107264-1-1.html
