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求助：allegro 封装更新后原先的地孔网络属性变了？
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请教：allegro 封装更新后，原先的地孔网络属性变成了3.3V，怎么能保持这些孔的网络不变?
refresh_symbol completed successfully, use Viewlog to review the log file.
Updating dynamic shape (1 of 6) 3.3V, Boundary/Inner Layer 3 @ (198.0000 0.2000) ...
Updating dynamic shape (2 of 6) Agnd, Boundary/Top @ (198.0000 0.2000) ...
Updating dynamic shape (3 of 6) Agnd, Boundary/Bottom @ (198.0000 0.2000) ...
Updating dynamic shape (4 of 6) Agnd, Boundary/Inner Layer 2 @ (198.0000 0.2000) ...
refresh_symbol completed successfully, use Viewlog to review the log file.
Updating dynamic shape (1 of 6) 3.3V, Boundary/Inner Layer 3 @ (198.0000 0.2000) ...
Updating dynamic shape (2 of 6) Agnd, Boundary/Top @ (198.0000 0.2000) ...
Updating dynamic shape (3 of 6) Agnd, Boundary/Bottom @ (198.0000 0.2000) ...
Updating dynamic shape (4 of 6) Agnd, Boundary/Inner Layer 2 @ (198.0000 0.2000) ...
没有人知道吗?其实就是怎么在重新铺铜的时候保持所有过孔的网络不变?
可以使用Logic——Net Logic 重新赋予PIN网络
不要打断 原来的连接 就不会变
检查原理图封装是不是跟新的PCB 封装对不上了才导致管脚属性变了
Cadence Allegro 培训套装，视频教学，直观易学
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